Comparing Circuit Connectivity Between All-Metal GDS Layouts
Abstract not provided.
Publications
Comparing Circuit Connectivity Between All-Metal GDS Layouts
Abstract not provided.
Different approaches for enhancing the thermal stability of Ge2Sb2Te5 films
Abstract not provided.
Heterogeneous Integration of III-V Photonics and Silicon Electronics for Advanced Optical Microsystems
Abstract not provided.
Heterogeneous Integration of III-V Photonics and Silicon Electronics for Advanced Optical Microsystems
Abstract not provided.
Spatial distribution of electrons on a super fluid helium charge-coupled device
Abstract not provided.
Extremely efficient clocked electron transfer on superfluid helium
Physical Review Letters
Abstract not provided.
Highly scalable control of electrons on superfluid helium
Nature
Abstract not provided.
Cryogenic CMOS circuits for single charge digital readout
Abstract not provided.
Cryogenic CMOS circuits for single charge digital readout
The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.
Charge transfer efficiency of electrons on helium
Abstract not provided.
Exploiting silicon chip technology for control of electrons on superfluid helium
Electrons on the surface of superfluid helium have extremely high mobilities and long predicted spin coherence times, making them ideal mobile qubits. Previous work has shown that electrons localized in helium filled channels can be reliably transported between multiple underlying gates. Silicon chips have been designed, fabricated, and post processed by reactive ion etching to leverage the large scale integration capabilities of silicon technology. These chips, which serve as substrates for the electrons on helium research, utilize silicon CMOS for on-chip signal amplification and multiplexing and the uppermost metal layers for defining the helium channels and applying electrical potentials for moving the electrons. We will discuss experimental results for on-chip circuitry and clocked electron transport along etched channels.
Development of lateral quantum dots with cryogenic silicon circuit assisted read-out
Abstract not provided.
Impact Ionization and Freeze-Out Model for Simulation of Low Gate Bias Kink Effect in SOI-MOSFETs Operating at Liquid He Temperature
Abstract not provided.
Brief Announcement: The Impact of Classical Electronics Constraints on a Solid-State Logical Qubit Memory
Abstract not provided.
CMOS Integrated single electron transistor electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out
2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately 1ns and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches. © 2008 IEEE.
Steps toward fabricating Cryogenic CMOS Compatible Single Electron Devices
Abstract not provided.
Steps toward on chip integration of single electron devices with CMOS electronics
Abstract not provided.
Z-Beamlet: a multi-KJ TW-class laser for backlit x-radiography applications on the Z-Accelerator
Abstract not provided.
X-ray optics on the Z-Accelerator backlit with the Z-Beamlet Laser & Z-Petawatt Laser systems
Abstract not provided.
20 Results