To advance the energy efficiency of general digital computing far beyond the thermodynamic limits that apply to conventional digital circuits will require utilizing the principles of reversible computing. It has been known since the early 1990s that reversible computing based on adiabatic switching is possible in CMOS, although almost all the “adiabatic” CMOS logic families in the literature are not actually fully adiabatic, which limits their achievable energy savings. The first CMOS logic style achieving truly, fully adiabatic operation if leakage was negligible (CRL) was not fully static, which led to practical engineering difficulties in the presence of certain nonidealities. Later, “static” adiabatic logic families were described, but they were not actually fully adiabatic, or fully static, and were much slower. In this paper, we describe a new logic family, Static 2-Level Adiabatic Logic (S2LAL), which is, to our knowledge, the first CMOS logic family that is both fully static, and truly, fully adiabatic (modulo leakage). In addition, S2LAL is, we think, the fastest possible such family (among fully pipelined sequential circuits), having a latency per logic stage of one tick (transition time), and a minimum clock period (initiation interval) of 8 ticks. S2LAL requires 8 phases of a trapezoidal power-clock waveform (plus constant power and ground references) to be supplied. We argue that, if implemented in a suitable fabrication process designed to aggressively minimize leakage, S2LAL should be capable of demonstrating a greater level of energy efficiency than any other semiconductor-based digital logic family known today.
This report describes an unpowered radio receiver capable of detecting and responding to weak signals transmit ted from comparatively long distances . This radio receiver offers key advantages over a short range zero - power radio receiver previously described in SAND2004 - 4610, A Zero - Power Radio Receiver . The device described here can be fabricated as an integrated circuit for use in portable wireless devices, as a wake - up circuit, or a s a stand - alone receiver operating in conjunction with identification decoders or other electroni cs. It builds on key sub - components developed at Sandia National Laboratories over many years. It uses surface acoustic wave (SAW) filter technology. It uses custom component design to enable the efficient use of small aperture antennas. This device uses a key component, the pyroelectric demodulator , covered by Sandia owned U.S. Patent 7397301, Pyroelectric Demodulating Detector [1] . This device is also described in Sandia owned U.S. Patent 97266446, Zero Power Receiver [2].
A power converter capable of converting the 48 V DC output of a photovoltaic panel into 120 V AC at up to 400 W has been demonstrated in a 40 cu. cm. (2.4 cu. in.) module, for a power density of greater than 160 W/cu. in. The module is enabled by the use of GaN and AlGaN field effect transistors (FETs) and diodes operating at higher power densities and higher switching frequencies than conventional silicon power devices. Typical photovoltaic panel converter/inverters have power densities ranging from 3.5-5.0 W/cu. in. and often make use of bulky, low frequency transformers. By using wide- and ultra-wide-bandgap switching devices, the operating frequency has been increased to 150 kHz, eliminating the need to use low frequency charge and current storage elements. The resulting size reduction demonstrates the significant possibilities that the adoption of GaN and AlGaN devices housed in small, 3D printed packages offers in the field of power electronics.
The effects of paralleling low-current vertical Gallium Nitride (v-GaN) diodes in a custom power module are reported. Four paralleled v-GaN diodes were demonstrated to operate in a buck converter at 1.3 Apeak (792 mArms) at 240 V and 15 kHz switching frequency. Additionally, high-fidelity SPICE simulations demonstrate the effects of device parameter variation on power sharing in a power module. The device parameters studied were found to have a sub-linear relationship with power sharing, indicating a relaxed need to bin parts for paralleling. This result is very encouraging for power electronics based on low-current v-GaN and demonstrates its potential for use in high-power systems.
The National Ecological Observatory Network (NEON) is an ambitious National Science Foundation sponsored project intended to accumulate and disseminate ecologically informative sensor data from sites among 20 distinct biomes found within the United States and Puerto Rico over a period of at least 30 years. These data are expected to provide valuable insights into the ecological impacts of climate change, land-use change, and invasive species in these various biomes, and thereby provide a scientific foundation for the decisions of future national, regional, and local policy makers. NEON's objectives are of substantial national and international importance, yet they must be achieved with limited resources. Sandia National Laboratories was therefore contracted to examine four areas of significant systems engineering concern; specifically, alternatives to commercial electrical utility power for remote operations, approaches to data acquisition and local data handling, protocols for secure long-distance data transmission, and processes and procedures for the introduction of new instruments and continuous improvement of the sensor network. The results of these preliminary systems engineering evaluations are presented, with a series of recommendations intended to optimize the efficiency and probability of long-term success for the NEON enterprise.
This report gives a description of the development of a Stable Local Oscillator (StaLO) multi-chip module (MCM). It is a follow-on report to SAND2006-6414, Stable Local Oscillator Microcircuit. The StaLO accepts a 100MHz input signal and produces output signals at 1.2, 3.3, and 3.6 GHz. The circuit is built as a multi-chip module (MCM), since it makes use of integrated circuit technologies in silicon and lithium niobate as well as discrete passive components. This report describes the development of an MCM-based version of the complete StaLO, fabricated on an alumina thick film hybrid substrate.
This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.
This report gives a description of the development of a Stable Local Oscillator (StaLO) Microcircuit. The StaLO accepts a 100MHz input signal and produces output signals at 1.2, 3.3, and 3.6 GHz. The circuit is built as a multi-chip module (MCM), since it makes use of integrated circuit technologies in silicon and lithium niobate as well as discrete passive components. The StaLO uses a comb generator followed by surface acoustic wave (SAW) filters. The comb generator creates a set of harmonic components of the 100MHz input signal. The SAW filters are narrow bandpass filters that are used to select the desired component and reject all others. The resulting circuit has very low sideband power levels and low phase noise (both less than -40dBc) that is limited primarily by the phase noise level of the input signal.