CTE (coefficient of thermal expansion) mismatch between two wafers has potential for brittle failure when large areas are bonded on top of one another (wafer to wafer or wafer to die bonds). To address this type of failure, we proposed patterning a polymer around metallic interconnects. For this project, utilized benzo cyclobutene (BCB) to form the bond and accommodate stress. For the metal interconnects, we used indium. To determine the benefits of utilizing BCB, mechanical shear testing of die bonding with just BCB were compared to die bonded just with oxide. These tests demonstrated that BCB, when cured for only 30 minutes and bonded at 200°C, the BCB was able to withstand shear forces similar to oxide. Furthermore, when the BCB did fail, it experienced a more ductile failure, allowing the silicon to crack, rather than shatter. To demonstrate the feasibility of using BCB between indium interconnects, wafers were pattered with layers of BCB with vias for indium or ENEPIG (electroless nickel, electroless palladium, immersion gold). Subsequently, these wafers were pattered with a variety of indium or ENEPIG interconnect pitches, diameters, and heights. These dies were bonded under a variety of conditions, and those that held a bond, were cross-sectioned and imaged. Images revealed that certain bonding conditions allow for interconnects and BCB to achieve a void-less bond and thus demonstrate that utilizing polymers in place of oxide is a feasible way to reduce CTE stress.
Plasmas formed in microscale gaps at DC and plasmas formed at radiofrequency (RF) both deviate in behavior compared to the classical Paschen curve, requiring lower voltage to achieve breakdown due to unique processes and dynamics, such as field emission and controlled rates of electron/ion interactions. Both regimes have been investigated independently, using high precision electrode positioning systems for microscale gaps or large, bulky emitters for RF. However, no comprehensive study of the synergistic phenomenon between the two exists. The behavior in such a combined system has the potential to reach sub-10 V breakdown, which combined with the unique electrical properties of microscale plasmas could enable a new class of RF switches, limiters and tuners.This work describes the design and fabrication of novel on-wafer microplasma devices with gaps as small as 100 nm to be operated at GHz frequencies. We used a dual-sacrificial layer process to create devices with microplasma gaps integrated into RF compatible 50 Ω coplanar waveguide transmission lines, which will allow this coupled behaviour to be studied for the first time. These devices are modelled using conventional RF simulations as well as the Sandia code, EMPIRE, which is capable of modelling the breakdown and formation of plasma in microscale gaps driven by high frequencies. Synchronous evaluation of the modelled electrical and breakdown behaviour is used to define device structures, predict behaviour and corroborate results. We further report preliminary independent testing of the microscale gap and RF behaviour. DC testing shows modified-Paschen curve behaviour for plasma gaps at and below four microns, demonstrating decreased breakdown voltage with reduced gap size. Additionally, preliminary S-parameter measurements of as-prepared and connectorized devices have elucidated RF device behaviour. Together, these results provide baseline data that enables future experiments as well as discussion of projected performance and applications for these unique devices.
High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μm diameter TSVs, etched into a 625 μm thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO4-H2SO4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.
In this study we examine a split-foundry multilevel application specific integrated circuit (ASIC) Si-interposer and die bonded using the direct bond interface (DBI) process, in addition to shortloop vehicles. The designs have been subject to relaxed pattern density rules, and exhibit chemical mechanical planarization (CMP) systematic process issues of varying degrees. We find that the interconnect formation is robust against moderate dielectric thickness variation, as well as a moderate degree of copper corrosion. We discuss and demonstrate various CMP methods which have a clear and repeatable impact. Pattern density effects and defectivity on the bond quality are examined using focused ion beam scanning electron microscope (FIB-SEM) images at the feature scale (sub 100 um) and intra-die scale (few mm). Impact to the CMP performance, including plug recess, and defectivity are discussed.
Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.
Heterogeneous Integration (HI) may enable optoelectronic transceivers for short-range and long-range radio frequency (RF) photonic interconnect using wavelength-division multiplexing (WDM) to aggregate signals, provide galvanic isolation, and reduce crosstalk and interference. Integration of silicon Complementary Metal-Oxide-Semiconductor (CMOS) electronics with InGaAsP compound semiconductor photonics provides the potential for high-performance microsystems that combine complex electronic functions with optoelectronic capabilities from rich bandgap engineering opportunities, and intimate integration allows short interconnects for lower power and latency. The dominant pure-play foundry model plus the differences in materials and processes between these technologies dictate separate fabrication of the devices followed by integration of individual die, presenting unique challenges in die preparation, metallization, and bumping, especially as interconnect densities increase. In this paper, we describe progress towards realizing an S-band WDM RF photonic link combining 180 nm silicon CMOS electronics with InGaAsP integrated optoelectronics, using HI processes and approaches that scale into microwave and millimeter-wave frequencies.