Publications

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A sidewall activation process was optimized for buried magnesium-doped p-GaN layers yielding a significant reduction in tunnel junction-enabled light emitting diode (LED) forward voltage. This buried activation enabled the realization of cascaded blue LEDs with fully transparent GaN homojunction tunnel junctions. The initial optimization of buried p-GaN activation was performed on PN junctions grown by metal organic chemical vapor deposition (MOCVD) buried under hybrid tunnel junctions grown by MOCVD and molecular beam epitaxy. Next the activation process was implemented in cascaded blue LEDs emitting at 450 nm, which were enabled by fully transparent GaN homojunction tunnel junctions. The tunnel junction-enabled multi-active region blue LEDs were grown monolithically by MOCVD. This work demonstrates a state-of-the-art tunnel junction-enabled cascaded LED utilizing homojunction tunnel junctions which do not contain any heterojunction interface.

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GaN p-n diodes were formed by selective area regrowth on freestanding GaN substrates using a dry etch, followed by post-etch surface treatment to reduce etch-induced defects, and subsequent regrowth into wells. Etched-and-regrown diodes with a 150 μm diameter achieved 840 V operation at 0.5 A/cm2 reverse current leakage and a specific on-resistance of 1.2 mΩ·cm2. Etched-and-regrown diodes were compared with planar, regrown diodes without etching on the same wafer. Both types of diodes exhibited similar forward and reverse electrical characteristics, which indicate that etch-induced defectivity of the junction was sufficiently mitigated so as not to be the primary cause for leakage. An area dependence for forward and reverse leakage current density was observed, suggesting that the mesa sidewall provided a leakage path.

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Impacts of silicon, carbon, and oxygen interfacial impurities on the performance of high-voltage vertical GaN-based p–n diodes are investigated. The results indicate that moderate levels (≈5 × 10¹⁷ cm^-3) of all interfacial impurities lead to reverse blocking voltages (V_b) greater than 200 V at 1 μA cm^-2 and forward leakage of less than 1 µA cm^-2 at 1.7 V. At higher interfacial impurity levels, the performance of the diodes becomes compromised. Herein, it is concluded that each impurity has a different effect on the device performance. For example, a high carbon spike at the junction correlates with high off-state leakage current in forward bias (≈100× higher forward leakage current compared with a reference diode), whereas the reverse bias behavior is not severely affected (> 200 V at 1 μA cm^-2). High silicon and oxygen spikes at the junction strongly affect the reverse leakage currents (≈ 1–10 V at 1 μA cm^-2). Regrown diodes with impurity (silicon, oxygen, and carbon) levels below 5 × 10¹⁷ cm^-3 show comparable forward and reverse results with the reference continuously grown diodes. The effect of the regrowth interface position relative to the metallurgical junction on the diode performance is also discussed.

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The impact of dry-etch-induced defects on the electrical performance of regrown, c-plane, GaN p-n diodes where the p-GaN layer is formed by epitaxial regrowth using metal-organic, chemical-vapor deposition was investigated. Diode leakage increased significantly for etched-and-regrown diodes compared to continuously grown diodes, suggesting a defect-mediated leakage mechanism. Deep level optical spectroscopy (DLOS) techniques were used to identify energy levels and densities of defect states to understand etch-induced damage in regrown devices. DLOS results showed the creation of an emergent, mid-gap defect state at 1.90 eV below the conduction band edge for etched-and-regrown diodes. Reduction in both the reverse leakage and the concentration of the 1.90 eV mid-gap state was achieved using a wet chemical treatment on the etched surface before regrowth, suggesting that the 1.90 eV deep level contributes to increased leakage and premature breakdown but can be mitigated with proper post-etch treatments to achieve >600 V reverse breakdown operation.

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Edge termination for vertical power devices presents a significant challenge, as improper termination can result in devices with a breakdown voltage significantly less than the ideal infinite-planar case. Edge termination for vertical GaN devices is particularly challenging due to limitations in ion implantation for GaN, and as such this work investigates a bevel edge termination technique that does not require implantation and has proven to be effective for Si and SiC power devices. However, due to key differences between GaN versus Si and SiC p-n junctions (specifically, a grown versus an implanted junction), this technology needs to be reevaluated for GaN. Simulation results suggest that by leveraging the effective bevel angle relationship, a 10-15° physical bevel angle can yield devices with 85-90% of the ideal breakdown voltage. Results are presented for a negative bevel edge termination on an ideally 2 kV vertical GaN p-n diode.

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