Publications

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The construction of high-fidelity control fields that are robust to control, system, and/or surrounding environment uncertainties is a crucial objective for quantum information processing. Using the two-state Landau-Zener model for illustrative simulations of a controlled qubit, we generate optimal controls for π/2 and π pulses and investigate their inherent robustness to uncertainty in the magnitude of the drift Hamiltonian. Next, we construct a quantum-control protocol to improve system-drift robustness by combining environment-decoupling pulse criteria and optimal control theory for unitary operations. By perturbatively expanding the unitary time-evolution operator for an open quantum system, previous analysis of environment-decoupling control pulses has calculated explicit control-field criteria to suppress environment-induced errors up to (but not including) third order from π/2 and π pulses. We systematically integrate this criteria with optimal control theory, incorporating an estimate of the uncertain parameter to produce improvements in gate fidelity and robustness, demonstrated via a numerical example based on double quantum dot qubits. For the qubit model used in this work, postfacto analysis of the resulting controls suggests that realistic control-field fluctuations and noise may contribute just as significantly to gate errors as system and environment fluctuations.

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We present the Quantum Computer Aided Design (QCAD) simulator that targets modeling quantum devices, particularly Si double quantum dots (DQDs) developed for quantum computing. The simulator core includes Poisson, Schrodinger, and Configuration Interaction solvers which can be run individually or combined self-consistently. The simulator is built upon Sandia-developed Trilinos and Albany components, and is interfaced with the Dakota optimization tool. It is being developed for seamless integration, high flexibility and throughput, and is intended to be open source. The QCAD tool has been used to simulate a large number of fabricated silicon DQDs and has provided fast feedback for design comparison and optimization.

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Qubits demonstrated using GaAs double quantum dots (DQD). The qubit basis states are the (1) singlet and (2) triplet stationary states. Long spin decoherence times in silicon spurs translation of GaAs qubit in to silicon. In the near term the goals are: (1) Develop surface gate enhancement mode double quantum dots (MOS & strained-Si/SiGe) to demonstrate few electrons and spin read-out and to examine impurity doped quantum-dots as an alternative architecture; (2) Use mobility, C-V, ESR, quantum dot performance & modeling to feedback and improve upon processing, this includes development of atomic precision fabrication at SNL; (3) Examine integrated electronics approaches to RF-SET; (4) Use combinations of numerical packages for multi-scale simulation of quantum dot systems (NEMO3D, EMT, TCAD, SPICE); and (5) Continue micro-architecture evaluation for different device and transport architectures.

We have compared simulations using solutions of Poisson's equation to detailed capacitance measurements on a double quantum dot structure. We tabulate the results and show which cases show good agreement and which do not. The capacitance values are also compared to those calculated by a solution of Laplace's equation. Electron density is plotted and discussed. In order to understand relevant potential barriers we compare simulations at 50 Kelvin to simulations at 15 Kelvin. We show that the charge density does not differ greatly, but that the conduction band potential does. However, a method of estimating the potential at 0 Kelvin based on the charge distribution at 50 Kelvin is shown to be close to the potential at 15 Kelvin. This method was used to estimate potential barriers at 0 Kelvin in two quantum dot structures.

We report low-temperature transport measurements of a silicon metal-oxide-semiconductor (MOS) double quantum dot (DQD). In contrast to previously reported measurements of DQD's in Si MOS structures, our device has a lateral gate geometry very similar to that used by Petta et al. to demonstrate coherent manipulation of single electron spins. This gate design provides a high degree of tunability, allowing for independent control over individual dot occupation and tunnel barriers, as well as the ability to use nearby constrictions to sense dot charge occupation. Comparison of experimentally extracted capacitances between the dot and nearby gates with electrostatic modeling demonstrates the presence of disorder and the ability to partially compensate for this disorder by adjustment of gate voltages. We experimentally show gate-controlled tuning of the interdot coupling over a wide range of energies, an important step towards potential quantum computing applications.

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We fabricated a split-gate defined point contact in a double gate enhancement mode Si-MOS device, and implanted Sb donor atoms using a self-aligned process. E-beam lithography in combination with a timed implant gives us excellent control over the placement of dopant atoms, and acts as a stepping stone to focused ion beam implantation of single donors. Our approach allows us considerable latitude in experimental design in-situ. We have identified two resonance conditions in the point contact conductance as a function of split gate voltage. Using tunneling spectroscopy, we probed their electronic structure as a function of temperature and magnetic field. We also determine the capacitive coupling between the resonant feature and several gates. Comparison between experimental values and extensive quasi-classical simulations constrain the location and energy of the resonant level. We discuss our results and how they may apply to resonant tunneling through a single donor.

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The observation and characterization of a single atom system in silicon is a significant landmark in half a century of device miniaturization, and presents an important new laboratory for fundamental quantum and atomic physics. We compare with multi-million atom tight binding (TB) calculations the measurements of the spectrum of a single two-electron (2e) atom system in silicon - a negatively charged (D-) gated Arsenic donor in a FinFET. The TB method captures accurate single electron eigenstates of the device taking into account device geometry, donor potentials, applied fields, interfaces, and the full host bandstructure. In a previous work, the depths and fields of As donors in six device samples were established through excited state spectroscopy of the D0 electron and comparison with TB calculations. Using self-consistent field (SCF) TB, we computed the charging energies of the D- electron for the same six device samples, and found good agreement with the measurements. Although a bulk donor has only a bound singlet ground state and a charging energy of about 40 meV, calculations show that a gated donor near an interface can have a reduced charging energy and bound excited states in the D- spectrum. Measurements indeed reveal reduced charging energies and bound 2e excited states, at least one of which is a triplet. The calculations also show the influence of the host valley physics in the two-electron spectrum of the donor.

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The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

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Constructing high-fidelity control pulses that are robust to control and system/environment fluctuations is a crucial objective for quantum information processing (QIP). We combine dynamical decoupling (DD) with optimal control (OC) to identify control pulses that achieve this objective numerically. Previous DD work has shown that general errors up to (but not including) third order can be removed from {pi}- and {pi}/2-pulses without concatenation. By systematically integrating DD and OC, we are able to increase pulse fidelity beyond this limit. Our hybrid method of quantum control incorporates a newly-developed algorithm for robust OC, providing a nested DD-OC approach to generate robust controls. Motivated by solid-state QIP, we also incorporate relevant experimental constraints into this DD-OC formalism. To demonstrate the advantage of our approach, the resulting quantum controls are compared to previous DD results in open and uncertain model systems.

Development of silicon, enhancement mode nanostructures for solid-state quantum computing will be described. A primary motivation of this research is the recent unprecedented manipulation of single electron spins in GaAs quantum dots, which has been used to demonstrate a quantum bit. Long spin decoherence times are predicted possible in silicon qubits. This talk will focus on silicon enhancement mode quantum dot structures that emulate the GaAs lateral quantum dot qubit but use an enhancement mode field effect transistor (FET) structure. One critical concern for silicon quantum dots that use oxides as insulators in the FET structure is that defects in the metal oxide semiconductor (MOS) stack can produce both detrimental electrostatic and paramagnetic effects on the qubit. Understanding the implications of defects in the Si MOS system is also relevant for other qubit architectures that have nearby dielectric passivated surfaces. Stable, lithographically defined, single-period Coulomb-blockade and single-electron charge sensing in a quantum dot nanostructure using a MOS stack will be presented. A combination of characterization of defects, modeling and consideration of modified approaches that incorporate SiGe or donors provides guidance about the enhancement mode MOS approach for future qubits and quantum circuit micro-architecture.

Silicon is an ideal system for investigating single electron or isolated donor spins for quantum computation, due to long spin coherence times. Enhancement mode strained-silicon/silicon germanium (sSi/SiGe) devices would offer an as-yet untried path toward electron or electron/donor quantum dot systems. Thin, undoped SiGe dielectrics allow tight electrostatic confinement, as well as potential Lande g-factor engineered spin manipulation. In this talk we summarize recent progress toward sSi/SiGe enhancement mode devices on sSi on insulator, including characterization with X-ray diffraction and atomic force microscopy, as well as challenges faced and progress on integration of either top-down and bottom-up donor placement approaches in a sSi/SiGe enhancement mode structure.

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Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately 1ns and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches. © 2008 IEEE.

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There is significant interest in forming quantum bits (qubits) out of single electron devices for quantum information processing (QIP). Information can be encoded using properties like charge or spin. Spin is appealing because it is less strongly coupled to the solid-state environment so it is believed that the quantum state can better be preserved over longer times (i.e., that is longer decoherence times may be achieved). Long spin decoherence times would allow more complex qubit operations to be completed with higher accuracy. Recently spin qubits were demonstrated by several groups using electrostatically gated modulation doped GaAs double quantum dots (DQD) [1], which represented a significant breakthrough in the solid-state field. Although no Si spin qubit has been demonstrated to date, work on Si and SiGe based spin qubits is motivated by the observation that spin decoherence times can be significantly longer than in GaAs. Spin decoherence times in GaAs are in part limited by the random spectral diffusion of the non-zero nuclear spins of the Ga and As that couple to the electron spin through the hyperfine interaction. This effect can be greatly suppressed by using a semiconductor matrix with a near zero nuclear spin background. Near zero nuclear spin backgrounds can be engineered using Si by growing {sup 28}Si enriched epitaxy. In this talk, we will present fabrication details and electrical transport results of an accumulation mode double top gated Si metal insulator semiconductor (MIS) nanostructure, Fig 1 (a) & (b). We will describe how this single electron device structure represent a path towards forming a Si based spin qubit similar in design as that demonstrated in GaAs. Potential advantages of this novel qubit structure relative to previous approaches include the combination of: no doping (i.e., not modulation doped); variable two-dimensional electron gas (2DEG) density; CMOS compatible processes; and relatively small vertical length scales to achieve smaller dots. A primary concern in this structure is defects at the insulator-silicon interface. The Sandia National Laboratories 0.35 {micro}m fab line was used for critical processing steps including formation of the gate oxide to examine the utility of a standard CMOS quality oxide silicon interface for the purpose of fabricating Si qubits. Large area metal oxide silicon (MOS) structures showed a peak mobility of 15,000 cm{sup 2}/V-s at electron densities of {approx}1 x 10{sup 12} cm{sup -2} for an oxide thickness of 10 nm. Defect density measured using standard C-V techniques was found to be greater with decreasing oxide thickness suggesting a device design trade-off between oxide thickness and quantum dot size. The quantum dot structure is completed using electron beam lithography and poly-silicon etch to form the depletion gates, Fig 1 (a). The accumulation gate is added by introducing a second insulating Al{sub 2}O{sub 3} layer, deposited by atomic layer deposition, followed by an Al top gate deposition, Fig. 1 (b). Initial single electron transistor devices using SiO{sub 2} show significant disorder in structures with relatively large critical dimensions of the order of 200-300 nm, Fig 2. This is not uncommon for large silicon structures and has been cited in the literature [2]. Although smaller structures will likely minimize the effect of disorder and well controlled small Si SETs have been demonstrated [3], the design constraints presented by disorder combined with long term concerns about effects of defects on spin decoherence time (e.g., paramagnetic centers) motivates pursuit of a 2nd generation structure that uses a compound semiconductor approach, an epitaxial SiGe barrier as shown in Fig. 2 (c). SiGe may be used as an electron barrier when combined with tensilely strained Si. The introduction of strained-Si into the double top gated device structure, however, represents additional fabrication challenges. Thermal budget is potentially constrained due to concerns related to strain relaxation. Fabrication details related to the introduction of strained silicon on insulator and SiGe barrier formation into the Sandia National Laboratories 0.35 {micro}m fab line will also be presented.

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We describe the development of a novel silicon quantum bit (qubit) device architecture that involves using materials that are compatible with a Sandia National Laboratories (SNL) 0.35 mum complementary metal oxide semiconductor (CMOS) process intended to operate at 100 mK. We describe how the qubit structure can be integrated with CMOS electronics, which is believed to have advantages for critical functions like fast single electron electrometry for readout compared to current approaches using radio frequency techniques. Critical materials properties are reviewed and preliminary characterization of the SNL CMOS devices at 4.2 K is presented.

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There is increasing interest in development of high speed, low noise and readily fieldable near infrared (NIR) single photon detectors. InGaAs/InP Avalanche photodiodes (APD) operated in Geiger mode (GM) are a leading choice for NIR due to their preeminence in optical networking. After-pulsing is, however, a primary challenge to operating InGaAs/InP single photon detectors at high frequencies1. After-pulsing is the effect of charge being released from traps that trigger false ("dark") counts. To overcome this problem, hold-off times between detection windows are used to allow the traps to discharge to suppress after-pulsing. The hold-off time represents, however, an upper limit on detection frequency that shows degradation beginning at frequencies of ∼100 kHz in InGaAs/InP. Alternatively, germanium (Ge) single photon avalanche photodiodes (SPAD) have been reported to have more than an order of magnitude smaller charge trap densities than InGaAs/InP SPADs , which allowed them to be successfully operated with passive quenching2 (i.e., no gated hold off times necessary), which is not possible with InGaAs/InP SPADs, indicating a much weaker dark count dependence on hold-off time consistent with fewer charge traps. Despite these encouraging results suggesting a possible higher operating frequency limit for Ge SPADs, little has been reported on Ge SPAD performance at high frequencies presumably because previous work with Ge SPADs has been discouraged by a strong demand to work at 1550 nm. NIR SPADs require cooling, which in the case of Ge SPADs dramatically reduces the quantum efficiency of the Ge at 1550 nm. Recently, however, advantages to working at 1310 nm have been suggested which combined with a need to increase quantum bit rates for quantum key distribution (QKD) motivates examination of Ge detectors performance at very high detection rates where InGaAs/InP does not perform as well. Presented in this paper are measurements of a commercially available Ge APD operated at relatively short GM hold-off times to examine whether there are potential advantages to using Ge for 1310 nm single photon detection. A weaker after-pulsing dependence on frequency is observed offering initial indications of the potential that Ge APDs might provide better high frequency performance.

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The silicon microelectronics industry is the technological driver of modern society. The whole industry is built upon one major invention--the solid-state transistor. It has become clear that the conventional transistor technology is approaching its limitations. Recent years have seen the advent of magnetoelectronics and spintronics with combined magnetism and solid state electronics via spin-dependent transport process. In these novel devices, both charge and spin degree freedoms can be manipulated by external means. This leads to novel electronic functionalities that will greatly enhance the speed of information processing and memory storage density. The challenge lying ahead is to understand the new device physics, and control magnetic phenomena at nanometer length scales and in reduced dimensions. To meet this goal, we proposed the silicon nanocrystal system, because: (1) It is compatible with existing silicon fabrication technologies; (2) It has shown strong quantum confinement effects, which can modify the electric and optical properties through directly modifying the band structure; and (3) the spin-orbital coupling in silicon is very small, and for isotopic pure {sup 28}Si, the nuclear spin is zero. These will help to reduce the spin-decoherence channels. In the past fiscal year, we have studied the growth mechanism of silicon-nanocrystals embedded in silicon dioxide, their photoluminescence properties, and the Si-nanocrystal's magnetic properties in the presence of Mn-ion doping. Our results may demonstrate the first evidence of possible ferromagnetic orders in Mn-ion implanted silicon nanocrystals, which can lead to ultra-fast information process and ultra-dense magnetic memory applications.

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Demand for integration of optoelectronic functionality (e.g., optical interconnects) with silicon complementary metal oxide semiconductor (CMOS) technology has for many years motivated the investigation of low temperature (∼450°C) germanium deposition processes that may be integrated in to the back-end CMOS process flow. A common challenge to improving the germanium quality is the thermal budget of the in-situ bake, which is used to reduce defect forming oxygen and carbon surface residues [1, 2]. Typical cleaning temperatures to remove significant concentrations of oxygen and carbon have been reported to be approximately 750°C for thermal hydrogen bakes in standard chemical vapor deposition chambers [3]. Germanium device performance using lower peak in-situ cleans (i.e., ∼450°C) has been hampered by additional crystal defectivity, although epitaxy is possible with out complete removal of oxygen and carbon at lower temperatures [4]. Plasma enhanced chemical vapor deposition (PECVD) is used to reduce the processing temperature. Hydrogen plasma assisted in-situ surface preparation of epitaxy has been shown to reduce both carbon and oxygen concentrations and enable epitaxial growth at temperatures as low as ∼150°C [5,6]. The hydrogen is believed to help produce volatile Si-O and H2O species in the removal of oxygen, although typically this is not reported to occur rapidly enough to completely clear the surface of all oxygen until ∼550°C. In this paper, we describe the use of an in-situ argon/germane high density plasma to help initiate germanium epitaxy on silicon using a peak temperature of approximately 460°C, Germanium is believed to readily break Si-O bonds to form more volatile Ge-O [7-9], therefore, argon/germane plasmas offer the potential to reduce the necessary in-situ clean temperature while obtaining similar results as hydrogen in-situ cleans. To the authors knowledge this report is also the first demonstration of germanium epitaxy on silicon using this commercially available high density plasma chamber configuration instead of, for example, remote or electron cyclotron resonance configurations. © 2006 Materials Research Society.