The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.
Constructing high-fidelity control pulses that are robust to control and system/environment fluctuations is a crucial objective for quantum information processing (QIP). We combine dynamical decoupling (DD) with optimal control (OC) to identify control pulses that achieve this objective numerically. Previous DD work has shown that general errors up to (but not including) third order can be removed from {pi}- and {pi}/2-pulses without concatenation. By systematically integrating DD and OC, we are able to increase pulse fidelity beyond this limit. Our hybrid method of quantum control incorporates a newly-developed algorithm for robust OC, providing a nested DD-OC approach to generate robust controls. Motivated by solid-state QIP, we also incorporate relevant experimental constraints into this DD-OC formalism. To demonstrate the advantage of our approach, the resulting quantum controls are compared to previous DD results in open and uncertain model systems.
Development of silicon, enhancement mode nanostructures for solid-state quantum computing will be described. A primary motivation of this research is the recent unprecedented manipulation of single electron spins in GaAs quantum dots, which has been used to demonstrate a quantum bit. Long spin decoherence times are predicted possible in silicon qubits. This talk will focus on silicon enhancement mode quantum dot structures that emulate the GaAs lateral quantum dot qubit but use an enhancement mode field effect transistor (FET) structure. One critical concern for silicon quantum dots that use oxides as insulators in the FET structure is that defects in the metal oxide semiconductor (MOS) stack can produce both detrimental electrostatic and paramagnetic effects on the qubit. Understanding the implications of defects in the Si MOS system is also relevant for other qubit architectures that have nearby dielectric passivated surfaces. Stable, lithographically defined, single-period Coulomb-blockade and single-electron charge sensing in a quantum dot nanostructure using a MOS stack will be presented. A combination of characterization of defects, modeling and consideration of modified approaches that incorporate SiGe or donors provides guidance about the enhancement mode MOS approach for future qubits and quantum circuit micro-architecture.
Silicon is an ideal system for investigating single electron or isolated donor spins for quantum computation, due to long spin coherence times. Enhancement mode strained-silicon/silicon germanium (sSi/SiGe) devices would offer an as-yet untried path toward electron or electron/donor quantum dot systems. Thin, undoped SiGe dielectrics allow tight electrostatic confinement, as well as potential Lande g-factor engineered spin manipulation. In this talk we summarize recent progress toward sSi/SiGe enhancement mode devices on sSi on insulator, including characterization with X-ray diffraction and atomic force microscopy, as well as challenges faced and progress on integration of either top-down and bottom-up donor placement approaches in a sSi/SiGe enhancement mode structure.
There is significant interest in forming quantum bits (qubits) out of single electron devices for quantum information processing (QIP). Information can be encoded using properties like charge or spin. Spin is appealing because it is less strongly coupled to the solid-state environment so it is believed that the quantum state can better be preserved over longer times (i.e., that is longer decoherence times may be achieved). Long spin decoherence times would allow more complex qubit operations to be completed with higher accuracy. Recently spin qubits were demonstrated by several groups using electrostatically gated modulation doped GaAs double quantum dots (DQD) [1], which represented a significant breakthrough in the solid-state field. Although no Si spin qubit has been demonstrated to date, work on Si and SiGe based spin qubits is motivated by the observation that spin decoherence times can be significantly longer than in GaAs. Spin decoherence times in GaAs are in part limited by the random spectral diffusion of the non-zero nuclear spins of the Ga and As that couple to the electron spin through the hyperfine interaction. This effect can be greatly suppressed by using a semiconductor matrix with a near zero nuclear spin background. Near zero nuclear spin backgrounds can be engineered using Si by growing {sup 28}Si enriched epitaxy. In this talk, we will present fabrication details and electrical transport results of an accumulation mode double top gated Si metal insulator semiconductor (MIS) nanostructure, Fig 1 (a) & (b). We will describe how this single electron device structure represent a path towards forming a Si based spin qubit similar in design as that demonstrated in GaAs. Potential advantages of this novel qubit structure relative to previous approaches include the combination of: no doping (i.e., not modulation doped); variable two-dimensional electron gas (2DEG) density; CMOS compatible processes; and relatively small vertical length scales to achieve smaller dots. A primary concern in this structure is defects at the insulator-silicon interface. The Sandia National Laboratories 0.35 {micro}m fab line was used for critical processing steps including formation of the gate oxide to examine the utility of a standard CMOS quality oxide silicon interface for the purpose of fabricating Si qubits. Large area metal oxide silicon (MOS) structures showed a peak mobility of 15,000 cm{sup 2}/V-s at electron densities of {approx}1 x 10{sup 12} cm{sup -2} for an oxide thickness of 10 nm. Defect density measured using standard C-V techniques was found to be greater with decreasing oxide thickness suggesting a device design trade-off between oxide thickness and quantum dot size. The quantum dot structure is completed using electron beam lithography and poly-silicon etch to form the depletion gates, Fig 1 (a). The accumulation gate is added by introducing a second insulating Al{sub 2}O{sub 3} layer, deposited by atomic layer deposition, followed by an Al top gate deposition, Fig. 1 (b). Initial single electron transistor devices using SiO{sub 2} show significant disorder in structures with relatively large critical dimensions of the order of 200-300 nm, Fig 2. This is not uncommon for large silicon structures and has been cited in the literature [2]. Although smaller structures will likely minimize the effect of disorder and well controlled small Si SETs have been demonstrated [3], the design constraints presented by disorder combined with long term concerns about effects of defects on spin decoherence time (e.g., paramagnetic centers) motivates pursuit of a 2nd generation structure that uses a compound semiconductor approach, an epitaxial SiGe barrier as shown in Fig. 2 (c). SiGe may be used as an electron barrier when combined with tensilely strained Si. The introduction of strained-Si into the double top gated device structure, however, represents additional fabrication challenges. Thermal budget is potentially constrained due to concerns related to strain relaxation. Fabrication details related to the introduction of strained silicon on insulator and SiGe barrier formation into the Sandia National Laboratories 0.35 {micro}m fab line will also be presented.
We describe the development of a novel silicon quantum bit (qubit) device architecture that involves using materials that are compatible with a Sandia National Laboratories (SNL) 0.35 mum complementary metal oxide semiconductor (CMOS) process intended to operate at 100 mK. We describe how the qubit structure can be integrated with CMOS electronics, which is believed to have advantages for critical functions like fast single electron electrometry for readout compared to current approaches using radio frequency techniques. Critical materials properties are reviewed and preliminary characterization of the SNL CMOS devices at 4.2 K is presented.
There is increasing interest in development of high speed, low noise and readily fieldable near infrared (NIR) single photon detectors. InGaAs/InP Avalanche photodiodes (APD) operated in Geiger mode (GM) are a leading choice for NIR due to their preeminence in optical networking. After-pulsing is, however, a primary challenge to operating InGaAs/InP single photon detectors at high frequencies1. After-pulsing is the effect of charge being released from traps that trigger false ("dark") counts. To overcome this problem, hold-off times between detection windows are used to allow the traps to discharge to suppress after-pulsing. The hold-off time represents, however, an upper limit on detection frequency that shows degradation beginning at frequencies of ∼100 kHz in InGaAs/InP. Alternatively, germanium (Ge) single photon avalanche photodiodes (SPAD) have been reported to have more than an order of magnitude smaller charge trap densities than InGaAs/InP SPADs , which allowed them to be successfully operated with passive quenching2 (i.e., no gated hold off times necessary), which is not possible with InGaAs/InP SPADs, indicating a much weaker dark count dependence on hold-off time consistent with fewer charge traps. Despite these encouraging results suggesting a possible higher operating frequency limit for Ge SPADs, little has been reported on Ge SPAD performance at high frequencies presumably because previous work with Ge SPADs has been discouraged by a strong demand to work at 1550 nm. NIR SPADs require cooling, which in the case of Ge SPADs dramatically reduces the quantum efficiency of the Ge at 1550 nm. Recently, however, advantages to working at 1310 nm have been suggested which combined with a need to increase quantum bit rates for quantum key distribution (QKD) motivates examination of Ge detectors performance at very high detection rates where InGaAs/InP does not perform as well. Presented in this paper are measurements of a commercially available Ge APD operated at relatively short GM hold-off times to examine whether there are potential advantages to using Ge for 1310 nm single photon detection. A weaker after-pulsing dependence on frequency is observed offering initial indications of the potential that Ge APDs might provide better high frequency performance.