Publications

Large and unexpected radiation-induced voltage shifts have been observed for some MOS technologies exposed to moisture. The mechanisms for these large voltage shifts and their implications for long-term aging are discussed.

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We irradiated floating gate (FG) memories with NOR and NAND architecture by using different TID sources, including 2 MeV, 98 MeV, and 105 MeV protons, X-rays, and γ-rays. Two classes of phenomena are responsible for charge loss from programmed FGs: the first is charge generation, recombination, and transport in the dielectrics, while the second is the emission of electrons above the oxide band. Charge loss from programmed FGs irradiated with protons of different energy closely tracks results from γ-rays, whereas the use of X-rays results in dose enhancement effects. © 2007 IEEE.

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The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80°C after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents. © 2006 IEEE.

The type of final chip passivation layer used to fabricate linear bipolar circuits can have a major impact on the total dose hardness of some circuits. It is demonstrated that National Semiconductor Corporation linear bipolar devices fabricated with only an amorphous silicon carbide passivation layer do not exhibit enhanced low-dose-rate sensitivity (ELDRS), while devices from the same production lot fabricated with other types of passivation layers are ELDRS sensitive. SiC passivation possesses mechanical, electrical and chemical properties that make it compatible with linear device fabrication processes. These properties of SiC passivation layers, combined with the excellent radiation response of devices passivated with SiC, make SiC passivation layers a very attractive choice for devices packaged in either ceramic or plastic-encapsulated packages for use in space environments. © 2006 IEEE.

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The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton energies and temperature. SRAMs from five different vendors were irradiated at proton energies from 20 to 500 MeV and at temperatures of 25° and 85°C. For the SRAMs and radiation conditions examined in this work, proton energy SEL thresholds varied from as low as 20 MeV to as high as 490 MeV. To gain insight into the observed effects, the heavy-ion SEL linear energy transfer (LET) thresholds of the SRAMs were measured and compared to high-energy transport calculations of proton interactions with different materials. For some SRAMs that showed proton-induced SEL, the heavy-ion SEL threshold LET was as high as 25 MeV-cm 2/mg. Proton interactions with Si cannot generate nuclear recoils with LETs this large. Our nuclear scattering calculations suggest that the nuclear recoils are generated by proton interactions with tungsten. Tungsten plugs are commonly used in most high-density ICs fabricated today, including SRAMs. These results demonstrate that for system applications where latchups cannot be tolerated, SEL hardness assurance testing should be performed at a proton energy at least as high as the highest proton energy present in the system environment. Moreover, the best procedure to ensure that ICs will be latchup free in proton environments may be to use a heavy-ion source with LETs ≥40 MeV-cm 2/mg. © 2005 IEEE.

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO{sub 2}) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.

This paper investigates the transient response of 50-nm gate length fully and partially depleted SOI and bulk devices to pulsed laser and heavy ion microbeam irradiations. The measured transient signals on 50-nm fully depleted devices are very short, and the collected charge is small compared to older 0.25-{micro}m generation SOI and bulk devices. We analyze in detail the influence of the SOI architecture (fully or partially depleted) on the pulse duration and the amount of bipolar amplification. For bulk devices, the doping engineering is shown to have large effects on the duration of the transient signals and on the charge collection efficiency.

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Eliminating radiation-induced parasitic leakage paths in integrated circuits (ICs) is key to improving their total dose hardness. Semiconductor manufacturers can use a combination of design and/or process techniques to eliminate known radiation-induced parasitic leakage paths. However, unknown or critical radiation-induced parasitic leakage may still exist on fully processed ICs and it is extremely difficult (if not impossible) to identify these leakage paths based on radiation induced parametric degradation. We show that light emission microscopy can be used to identify the location of radiation-induced parasitic leakage paths in ICs. This is illustrated by using light emission microscopy to find radiation-induced parasitic leakage paths in partially-depleted silicon on insulator static random-access memories (SRAMs). Once leakage paths were identified, modifications were made to the SRAM design to improve the total dose radiation hardness of the SRAMs. Light emission microscopy should prove to be an important tool for the development of future radiation hardened technologies and devices.

Microelectronic devices in satellites and spacecraft are exposed to high energy cosmic radiation. Furthermore, Earth-based electronics can be affected by terrestrial radiation. The radiation causes a variety of Single Event Effects (SEE) that can lead to failure of the devices. High energy heavy ion beams are being used to simulate both the cosmic and terrestrial radiation to study radiation effects and to ensure the reliability of electronic devices. Broad beam experiments can provide a measure of the radiation hardness of a device (SEE cross section) but they are unable to pinpoint the failing components in the circuit. A nuclear microbeam is an ideal tool to map SEE on a microscopic scale and find the circuit elements (transistors, capacitors, etc.) that are responsible for the failure of the device. In this paper a review of the latest radiation effects microscopy (REM) work at Sandia will be given. Different SEE mechanisms (Single Event Upset, Single Event Transient, etc.) and the methods to study them (Ion Beam Induced Charge (IBIC), Single Event Upset mapping, etc.) will be discussed. Several examples of using REM to study the basic effects of radiation in electronic devices and failure analysis of integrated circuits will be given.

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Implanting the buried oxide of silicon-on-insulator technologies can create electron traps throughout the buried oxide that can compensate the buildup of radiation-induced positive charge. These can be used as an effective method for total-dose hardening buried oxides in SOI devices. In this work, we show that implanting buried oxides can also create thermally activated metastable electron traps near the top Si/SiO2 border. These metastable electron traps can produce significant bias instabilities in the back-gate transistor characteristics and lead to threshold voltage instabilities in fully-depleted devices. © 2004 Elsevier B.V. All rights reserved.

This paper analyzes the collected charge in heavy ion irradiated MOS structures. The charge generated in the substrate induces a displacement effect which strongly depends on the capacitor structure. Networks of capacitors are particularly sensitive to charge sharing effects. This has important implications for the reliability of SOI and DRAMs which use isolation oxides as a key elementary structure. The buried oxide of presentday and future SOI technologies is thick enough to avoid a significant collection from displacement effects. On the other hand, the retention capacitors of trench DRAMs are particularly sensitive to charge release in the substrate. Charge collection on retention capacitors participate to the MBU sensitivity of DRAM.

Mechanisms for enhanced low-dose-rate sensitivity are described. In these mechanisms, bimolecular reactions dominate the kinetics at high dose rates thereby causing a sub-linear dependence on total dose, and this leads to a dose-rate dependence. These bimolecular mechanisms include electron-hole recombination, hydrogen recapture at hydrogen source sites, and hydrogen dimerization to form hydrogen molecules. The essence of each of these mechanisms is the dominance of the bimolecular reactions over the radiolysis reaction at high dose rates. However, at low dose rates, the radiolysis reaction dominates leading to a maximum effect of the radiation.

We examine the total-dose radiation response of capacitors and transistors with stacked Al{sub 2}O{sub 3} on oxynitride gate dielectrics with Al and poly-Si gates after irradiation with 10 keV X-rays. The midgap voltage shift increases monotonically with dose and depends strongly on both Al{sub 2}O{sub 3} and SiO{sub x}N{sub y} thickness. The thinnest dielectrics, of most interest to industry, are extremely hard to ionizing irradiation, exhibiting only {approx}50 mV of shift at a total dose of 10 Mrad(SiO{sub 2}) for the worst case bias condition. Oxygen anneals are found to improve the total dose radiation response by {approx}50% and induce a small amount of capacitance-voltage hysteresis. Al{sub 2}O{sub 3}/SiO{sub x}N{sub y} dielectrics which receive a {approx}1000 C dopant activation anneal trap {approx}12% more of the initial charge than films annealed at 550 C. Charge pumping measurements show that the interface trap density decreases with dose up to 500 krad(SiO{sub 2}). This surprising result is discussed with respect to hydrogen effects in alternative dielectric materials, and may be the result of radiation-induced hydrogen passivation of some of the near-interfacial defects in these gate dielectrics.

It is shown that final chip passivation layers can have a significant impact on total dose hardness. A number of final chip passivation layers are evaluated to identify films that mitigate enhanced low-dose-rate sensitivity (ELDRS) in National Semiconductor Corporation's linear bipolar technologies. It is shown that devices fabricated with either a low temperature oxide or a tetraethyl ortho silicate passivation do not exhibit significant ELDRS effects up to 100 krad(SiO{sub 2}). Passivation studies on CMOS SRAMs suggest that it is unlikely that the passivation layers (or processing tools) are acting as a new source of hydrogen, which could drift or diffuse into the oxide and increase ELDRS sensitivity. Instead, it is possible that the passivation layers affect the mechanical stress in the oxide, which may affect oxide trap properties and possibly the release and mobility of hydrogen. Correlations between mechanical stress induced by the passivation layers and radiation degradation are discussed.

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

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High-energy ion-irradiated 3.3-nm oxynitride film and 2.2-nm SiO₂-film MOS capacitors show premature breakdown during subsequent electrical stress. This degradation in breakdown increases with increasing ion linear energy transfer (LET), increasing ion fluence, and decreasing oxide thickness. We explain the reliability degradation due to high-energy ion-induced latent defects by a simple percolation model of conduction through SiO₂ layers with irradiation and/or electrical stress-induced defects. Monitoring the gate-leakage current reveals the presence of latent defects in the dielectric films. Finally, our results may be significant to future single-event effects and single-event gate rupture tests for MOS devices and ICs with ultrathin gate oxides.

Silicon-on-insulator (SOI) technology exhibits three main advantages over bulk silicon technology for use in radiation environments. (1) SOI devices are immune to latchup, (2) the volume of the sensitive region (body) and hence total charge collection per transient irradiation is much reduced in SOI devices and (3) the insulating layer blocks charge collection from the substrate (i.e., no funneling effect). This effectively raises the single event upset (SEU) threshold for the SOI device. However, despite their small active volume SOI devices are still vulnerable to single event effects (SEE). Inherent in the SOI transistor design is a parasitic npn bipolar junction transistor (BJT), where the source-body-drain acts as an emitter-base-collector BJT. An ion strike to a floating (not referenced to a specific potential) body creates a condition where the excess minority carriers in the drain-body cause the parasitic BJT to turn on and inject more charge into the drain than was deposited in the device by the ion. In extreme cases the floating body effect (FBE) can trigger a high-current state called single-event snapback (SES) where channel conduction is sustained indefinitely through regenerative electron-impact ionization near the drain junction. Tying the body to the source limits the emitter-base current and reduces the sensitivity of the device to single ion strikes. Unfortunately, the body-tie loses effectiveness with distance due to resistivity, and in regions far enough from the tie the BJT is still in effect. Using the Sandia nuclear microprobe we have created charge collection maps on Sandia CMOS6rs SOI FETs of varying channel widths. These devices have body ties at both ends of the channel region. Results clearly demonstrate that distance of the ion strike from the body tie has an inverse effect upon charge collection and SES sensitivity due to the resistivity of the channel. Experimental results compare well with DAVINCI simulations and electrically induced snapback thresholds. In addition, an intere sting saturation effect of SES versus the amount of injected charge is observed. © 2001 Elsevier Science B.V. All rights reserved.

The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.

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The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

Metal-oxide-silicon capacitors fabricated in a bi-polar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100 C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H{sup +} ions in the oxide and Si layers and the availability of holes in the Si depletion region. Capacitor data from unbiased irradiations were used to simulate the impact of acceptor neutralization on the current gain of an npn bipolar transistor. Neutralized acceptors near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may enhance radiation-induced degradation of linear circuits at elevated temperatures.

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Dopant deactivation at 100 C is measured in bipolar Si-SiO{sub 2} structures as a function of irradiation bias. The deactivation occurs most efficiently at small biases in depletion and is consistent with passivation and compensation mechanisms involving hydrogen.

SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed.

Large differences in charge buildup in SOI buried oxides can result between x-ray and Co-60 irradiations. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored.