HIGH-VOLTAGE ATMOSPHERIC BREAKDOWN ACROSS INTERVENING RUTILE DIELECTRICS
Abstract not provided.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Abstract not provided.
ECS Transactions
The increase in the magnitude of the threshold voltage of a positive-channel metal oxide semiconductor (PMOS) under negative gate biasing (negative bias temperature instability) is attributed to the build-up of charge in the gate insulator. We have studied the charging and discharging of nitrided SiO2 gate insulator field effect transistors and through the use of pseudo-DC and pulsed stressing methods, have extracted, at least, three charging components. These components are (a) the charging of interface states at the semiconductor/insulator boundary, (b) dynamically recoverable positive charging in the bulk' of the insulator, and (c) positive charging in the insulator, which can be eliminated' only by application of a positive electric field across the insulator. It is proposed that the charge elimination' in (c) arises via a charge neutralization process involving electron capture at switching traps, as opposed to de-trapping, and that this can be reversed by the application of a small negative field. © The Electrochemical Society.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Proposed for publication in IEEE Electron Device Letters.
Abstract not provided.
Abstract not provided.
Abstract not provided.
Digest of Technical Papers-IEEE International Pulsed Power Conference
Continuum calculations are used to understand the avalanche growth of electrical current in a composite insulator consisting of an air gap and a solid dielectic. The results show that trapped charge can quench the electrical breakdown. The results are compared with phenomena found in dielectric barrier discharge (DBD) devices. © 2011 IEEE.
IEEE Transactions on Nuclear Science
Low dose rate experiments on field-oxide-field-effect-transistors (FOXFETs) fabricated in a 90 nm CMOS technology indicate that there is a dose rate enhancement factor (EF) associated with radiation-induced degradation. One dimensional (1-D) numerical calculations are used to investigate the key mechanisms responsible for the dose rate dependent buildup of radiation-induced defects in shallow trench isolation (STI) oxides. Calculations of damage EF indicate that oxide thickness, distribution of hole traps and hole capture cross-section affect dose rate sensitivity. The dose rate sensitivity of STI oxides is compared with the sensitivity of bipolar base oxides using model calculations. © 2011 IEEE.
Abstract not provided.
Abstract not provided.
Abstract not provided.
This document summarizes the work done in our three-year LDRD project titled 'Physics of Intense, High Energy Radiation Effects.' This LDRD is focused on electrical effects of ionizing radiation at high dose-rates. One major thrust throughout the project has been the radiation-induced conductivity (RIC) produced by the ionizing radiation. Another important consideration has been the electrical effect of dose-enhanced radiation. This transient effect can produce an electromagnetic pulse (EMP). The unifying theme of the project has been the dielectric function. This quantity contains much of the physics covered in this project. For example, the work on transient electrical effects in radiation-induced conductivity (RIC) has been a key focus for the work on the EMP effects. This physics in contained in the dielectric function, which can also be expressed as a conductivity. The transient defects created during a radiation event are also contained, in principle. The energy loss lead the hot electrons and holes is given by the stopping power of ionizing radiation. This information is given by the inverse dielectric function. Finally, the short time atomistic phenomena caused by ionizing radiation can also be considered to be contained within the dielectric function. During the LDRD, meetings about the work were held every week. These discussions involved theorists, experimentalists and engineers. These discussions branched out into the work done in other projects. For example, the work on EMP effects had influence on another project focused on such phenomena in gases. Furthermore, the physics of radiation detectors and radiation dosimeters was often discussed, and these discussions had impact on related projects. Some LDRD-related documents are now stored on a sharepoint site (https://sharepoint.sandia.gov/sites/LDRD-REMS/default.aspx). In the remainder of this document the work is described in catergories but there is much overlap between the atomistic calculations, the continuum calculations and the experiments.
ECS Transactions
Negative bias temperature instability (NBTI) is an issue of critical importance as tile space electronics industry evolves because it may dominate tile reliability lifetime of space based assets. Understanding its physical origin is therefore essential in determining how best to search for methods of mitigation. It has been suggested that the magnitude of the effect is strongly dependent on circuit operation conditions (static or dynamic modes). In the present work, we examine the time constants related to the charging and recovery of trapped charged induced by NBTI in HfSiON and SiO2 gate dielectric devices at room temperature. ©The Electrochemical Society.
Negative bias temperature instability is an issue of critical importance as the space electronics industry evolves because it may dominate the reliability lifetime. Understanding its physical origin is therefore essential in determining how best to search for methods of mitigation. It has been suggested that the magnitude of the effect is strongly dependent on circuit operation conditions (static or dynamic modes). In the present work, we examine the time constants related to the charging and recovery of trapped charged induced by NBTI in HfSiON gate dielectric devices. In previous work, we avoided the issue of charge relaxation during acquisition of the I{sub ds}(V{sub gs}) curve by invoking a continuous stressing technique whereby {Delta}V{sub th} was extracted from a series of single point I{sub ds} measurements. This method relied heavily on determination of the initial value of the source-drain current (I{sub ds}{sup o}) prior to application of gate-source stress. In the present work we have used a new pulsed measurement system (Keithley SCS 4200-PIV) which not only removes this uncertainty but also permits dynamic measurements in which devices are AC stressed (Fig. 1a) or subjected to cycles of continued DC stresses followed by relaxation (Fig. 1b). We can now examine the charging and recovery characteristics of NBTI with higher precision than previously possible. We have performed NBTI stress experiments at room temperature on p-channel MOSFETs made with HfSiON gate dielectrics. In all cases the devices were stressed in the linear regime with V{sub ds}=-0.1V. We have defined two separate waveforms/pulse trains as illustrated in Fig 1. These were applied to the gate of the MOSFET. Firstly we examined the charging characteristics by applying an AC stress at 2.5MHz or 10Hz for different times. For a 50% duty cycle this corresponded to V{sub gs} = - 2V pulses for 200ns or 500ms followed by V{sub gs} = 0V pulses for 200ns or 500ms recovery respectively. In between 'bursts' of AC stress cycles, the I{sub ds}(V{sub gs}) characteristic in the range (-0.6V, -1.3V) was measured in 10.2 {micro}s. V{sub th} was extracted directly from this curve, or from a single I{sub ds} point normalized to the initial I{sub ds}{sup o} using our previous method. The resulting I{sub ds}/I{sub ds}{sup o} curves are compared; in Fig 2, the continuous stress results are included. In the second method, we examined the recovery dynamic by holding V{sub gs} = 0V for a finite amount of time (range 100 ns to 100 ms) following stress at V{sub gs} = - 2V for various times. In Fig 3 we compare |{Delta}V{sub th}(t)| results for recovery times of 100ms, 1ms, 100{micro}s, 50{micro}s, 25{micro}s, 10{micro}s, 100ns, and DC (i.e. no recovery) The data in Fig 2 shows that with a high frequency stress (2.5MHz) devices undergo significantly less (but finite) current degradation than devices stressed at 10Hz. This appears to be limited by charging and not by recovery. Fig 3 supports this hypothesis since for 100ns recovery periods, only a small percentage of the trapped charge relaxes. Detailed explanation of these experiments will be presented at the conference.