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Sensitivity analysis of a technique for the extraction of interface trap density in SiC MOSFETs from subthreshold characteristics

IEEE International Reliability Physics Symposium Proceedings

Hughart, David R.; Flicker, Jack D.; Atcitty, Stanley A.; Marinella, M.J.; Kaplar, Robert K.

A method for extracting interface trap density (DIT) from subthreshold I-V characteristics is used to analyze data on a SiC MOSFET stressed for thirty minutes at 175°C with a gate bias of-20 V. Without knowing the channel doping, the change in DIT can be calculated when referenced to an energy level correlated with the threshold voltage. © 2014 IEEE.

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TYPE Conference YEAR 2014
ScopusOSTIDOI

A CMOS Compatible, Forming Free TaOx ReRAM

ECS Transactions (Online)

Stevens, James E.; Mickel, Patrick R.; Hughart, David R.; Marinella, Matthew J.

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x105 cycle endurance.

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TYPE Journal Article YEAR 2013
OSTIDOI
Results 101–124 of 124
Results 101–124 of 124