Publications

npj Quantum Information

Sterk, Jonathan D.; Coakley, Henry J.; Goldberg, Joshua D.; Hietala, Vincent &.; Lechtenberg, Jason L.; McGuinness, Hayden J.; McMurtrey, Daniel L.; Parazzoli, Lambert P.; Van Der Wall, Jay W.; Stick, Daniel L.

Shuttling ions at high speed and with low motional excitation is essential for realizing fast and high-fidelity algorithms in many trapped-ion-based quantum computing architectures. Achieving such performance is challenging due to the sensitivity of an ion to electric fields and the unknown and imperfect environmental and control variables that create them. Here we implement a closed-loop optimization of the voltage waveforms that control the trajectory and axial frequency of an ion during transport in order to minimize the final motional excitation. The resulting waveforms realize fast round-trip transport of a trapped ion across multiple electrodes at speeds of 0.5 electrodes per microsecond (35 m∙s^-1 for a one-way transport of 210 μm in 6 s) with a maximum of 0.36 ± 0.08 mean quanta gain. This sub-quanta gain is independent of the phase of the secular motion at the distal location, obviating the need for an electric field impulse or time delay to eliminate the coherent motion.

McMurtrey, Daniel L.

Abstract not provided.

McMurtrey, Daniel L.; Hymel, Ross W.

Abstract not provided.

IEEE Aerospace Conference Proceedings

Johnson, Jonathan; Howes, William; Wirthlin, Michael; McMurtrey, Daniel L.; Caffrey, Michael; Graham, Paul; Morgan, Keith

It is well known that SRAM-based FPGAs are susceptible to single-event upsets (SEUs) in radiation environments. A variety of mitigation strategies have been demonstrated to provide appropriate mitigation and correction of SEUs in these environments. While full mitigation of SEUs is appropriate for some situations, some systems may tolerate SEUs as long as these upsets are detected quickly and correctly. These systems require effective error detection techniques rather than costly error correction methods. This work leverages a well-known error detection technique for FPGAs called duplication with compare (DWC). This technique has been shown to be very effective at quickly and accurately detecting SEUs using fault injection and radiation testing. ©2008 IEEE.