Maximum power handling, spike leakage, and failure mechanisms have been characterized for limiters based on the thermally triggered metal-insulator transition of vanadium dioxide. These attributes are determined by properties of the metal-insulator material such as on/off resistance ratio, geometric properties that determine the film resistance and the currentcarrying capability of the device, and thermal properties such as heatsinking and thermal coupling. A limiter with greater than 10 GHz of bandwidth demonstrated 0.5 dB loss, 27 dBm threshold power, 8 Watts blocking power, and 0.4 mJ spike leakage at frequencies near 2 GHz. A separate limiter optimized for high power blocked over 60 Watts of incident power with leakage less than 25 dBm after triggering. The power handling demonstrates promise for these limiter devices, and device optimization presents opportunities for additional improvement in spike leakage, response speed, and reliability.
Biasing a MEMS switch close to static-pull in reduces the modulation amplitude necessary to achieve resonant pull-in, but results in a highly nonlinear system. In this work, we present a new methodology that captures the essential dynamics and provides a prescription for achieving the optimal drive waveform which reduces the amplitude requirements of the modulation source. These findings are validated both experimentally and through numerical modeling.
Inductive coupling and matching networks are used to increase the bandwidth of filters realized with aluminum nitride contour-mode resonators. Filter bandwidth has been doubled using a wirebonded combination of a wafer-level-packaged resonator chip and a high-Q integrated inductor chip. The three-pole filters have a center frequency near 500 MHz, an area of 9 mm × 9 mm, insertion loss of < 5 dB for a bandwidth of 0.4%, and a resonator unloaded Q of 1600.
Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor $I$-$V$ characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e., positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. The suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III-V/Si heterogeneously integrated electronics.