Publications

Abstract not provided.

Abstract not provided.

Microsystem-Enabled Photovoltaic (MEPV) cells allow solar PV systems to take advantage of scaling benefits that occur as solar cells are reduced in size. We have developed MEPV cells that are 5 to 20 microns thick and down to 250 microns across. We have developed and demonstrated crystalline silicon (c-Si) cells with solar conversion efficiencies of 14.9%, and gallium arsenide (GaAs) cells with a conversion efficiency of 11.36%. In pursuing this work, we have identified over twenty scaling benefits that reduce PV system cost, improve performance, or allow new functionality. To create these cells, we have combined microfabrication techniques from various microsystem technologies. We have focused our development efforts on creating a process flow that uses standard equipment and standard wafer thicknesses, allows all high-temperature processing to be performed prior to release, and allows the remaining post-release wafer to be reprocessed and reused. The c-Si cell junctions are created using a backside point-contact PV cell process. The GaAs cells have an epitaxially grown junction. Despite the horizontal junction, these cells also are backside contacted. We provide recent developments and details for all steps of the process including junction creation, surface passivation, metallization, and release.

Vapor phase XeF{sub 2} has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF{sub 2} Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF{sub 2} vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO{sub 2}) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF{sub 2} etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO{sub 2}. The buried SiO{sub 2} was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO{sub 2}. FC polymer was deposited from C4F8 gas precursor in an inductively coupled plasma reactor, and SiO{sub 2} was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF{sub 2} was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF{sub 2} due to protection from the top SiO{sub 2} mask, sidewall passivation, and the buried SiO{sub 2} layer. Optimization of the XeF{sub 2} process and the sidewall passivation layers will be discussed. The advantages of releasing SOI devices with XeF{sub 2} include avoiding stiction, maintaining the integrity of the buried SiO{sub 2}, and simplifying the fabrication flow for thermally actuated devices.

We present a newly developed microsystem enabled, back-contacted, shade-free GaAs solar cell. Using microsystem tools, we created sturdy 3 {micro}m thick devices with lateral dimensions of 250 {micro}m, 500 {micro}m, 1 mm, and 2 mm. The fabrication procedure and the results of characterization tests are discussed. The highest efficiency cell had a lateral size of 500 {micro}m and a conversion efficiency of 10%, open circuit voltage of 0.9 V and a current density of 14.9 mA/cm{sup 2} under one-sun illumination.

We present a newly developed microsystem enabled, back-contacted, shade-free GaAs solar cell. Using microsystem tools, we created sturdy 3 {micro}m thick devices with lateral dimensions of 250 {micro}m, 500 {micro}m, 1 mm, and 2 mm. The fabrication procedure and the results of characterization tests are discussed. The highest efficiency cell had a lateral size of 500 {micro}m and a conversion efficiency of 10%, open circuit voltage of 0.9 V and a current density of 14.9 mA/cm{sup 2} under one-sun illumination.