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Advanced compound semiconductor and silicon fabrication techniques for next-generation solar power systems

ECS Transactions

Nielson, Gregory N.; Okandan, Murat O.; Cruz-Campa, Jose L.; Gupta, Vipin P.; Resnick, Paul J.; Sanchez, Carlos A.; Paap, Scott M.; Kim, B.; Sweatt, W.C.; Lentine, Anthony L.; Cederberg, Jeffrey G.; Tauke-Pedretti, Anna; Jared, B.H.; Anderson, Benjamin J.; Biefeld, Robert M.; Nelson, J.S.

Microsystem technologies have the potential to significantly improve the performance, reduce the cost, and extend the capabilities of solar power systems. These benefits are possible due to a number of significant beneficial scaling effects within solar cells, modules, and systems that are manifested as the size of solar cells decrease to the sub-millimeter range. To exploit these benefits, we are using advanced fabrication techniques to create solar cells from a variety of compound semiconductors and silicon that have lateral dimensions of 250 - 1000 μm and are 1 - 20 μm thick. These fabrication techniques come out of relatively mature microsystem technologies such as integrated circuits (IC) and microelectromechanical systems (MEMS) which provide added supply chain and scale-up benefits compared to even incumbent PV technologies. © The Electrochemical Society.

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Fabrication of lattice mismatched multijunction photovoltaic cells using 3D integration concepts

Conference Record of the IEEE Photovoltaic Specialists Conference

Cruz-Campa, Jose L.; Nielson, Gregory N.; Lentine, Anthony L.; Filatov, Anton A.; Resnick, Paul J.; Sanchez, Carlos A.; Rowen, Adam M.; Okandan, Murat O.; Gupta, Vipin P.; Nelson, Jeffrey S.

We present the experimental procedure to create lattice mismatched multijunction photovoltaic (PV) cells using 3D integration concepts. Lattice mismatched multijunction photovoltaic (PV) cells with decoupled electrical outputs could achieve higher efficiencies than current-matched monolithic devices. Growing lattice mismatched materials as a monolithic structure generates defects and decreases performance. We propose using methods from the integrated circuits and microsystems arena to produce the PV cell. The fabricated device consists of an ultrathin (6 μm) series connected InGaP/GaAs PV cell mechanically stacked on top of an electrically independent silicon cell. The InGaP/GaAs PV cell was processed to produce a small cell (750 μm) with back-contacts where all of the contacts sit at the same level. The dual junction and the silicon (c-Si) cell are electrically decoupled and the power from both cells is accessible through pads on the c-Si PV cell. Through this approach, we were able to fabricate a functional double junction PV cell mechanically attached to a c-Si PV cell with independent connections. © 2012 IEEE.

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Gallium nitride based logpile photonic crystals for visible lighting

Proceedings of SPIE - The International Society for Optical Engineering

Subramania, G.; Li, Q.; Lee, Y.J.; Figiel, J.J.; Sanchez, Carlos A.; Wang, George T.; Fischer, Arthur J.; Biswas, R.

Photonic crystals (PC) can fundamentally alter the emission behavior of light sources by suitably modifying the electromagnetic environment around them. Strong modulation of the photonic density of states especially by full threedimensional (3D) bandgap PCs, enables one to completely suppress emission in undesired wavelengths and directions while enhancing desired emission. This property of 3DPC to control spontaneous emission, opens up new regimes of light-matter interaction in particular, energy efficient and high brightness visible lighting. Therefore a 3DPC composed entirely of gallinum nitride (GaN), a key material used in visible light emitting diodes can dramatically impact solid state lighting. The following work demonstrates an all GaN logpile 3DPC with bandgap in the visible fabricated by a template directed epitaxial growth. © 2012 SPIE.

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Three wafer stacking for 3D integration

Ford, Christine L.; Greth, Karl D.; Hetherington, Dale L.; Sanchez, Carlos A.; Shinde, Subhash L.; Timon, Robert P.

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

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Results 26–50 of 56
Results 26–50 of 56