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XeF2 vapor phase silicon etch used in the fabrication of movable SOI structures

Shul, Randy J.; Bauer, Todd B.; Plut, Thomas A.; Sanchez, Carlos A.

Vapor phase XeF{sub 2} has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF{sub 2} Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF{sub 2} vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO{sub 2}) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF{sub 2} etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO{sub 2}. The buried SiO{sub 2} was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO{sub 2}. FC polymer was deposited from C4F8 gas precursor in an inductively coupled plasma reactor, and SiO{sub 2} was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF{sub 2} was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF{sub 2} due to protection from the top SiO{sub 2} mask, sidewall passivation, and the buried SiO{sub 2} layer. Optimization of the XeF{sub 2} process and the sidewall passivation layers will be discussed. The advantages of releasing SOI devices with XeF{sub 2} include avoiding stiction, maintaining the integrity of the buried SiO{sub 2}, and simplifying the fabrication flow for thermally actuated devices.

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TYPE Conference YEAR 2010
OSTI

Improved manufacturability of AlGaAs/GaAs Pnp heterojunction bipolar transistors

ECS Transactions

Clevenger, J.B.; Patrizi, G.A.; Peterson, T.C.; Cich, M.J.; Baca, A.G.; Klem, John F.; Plut, Thomas A.; Fortune, T.R.; Hightower, M.S.; Torres, D.; Hawkins, Samuel D.; Sullivan, Charles T.

Specially designed Pnp heterojunction bipolar transistors (HBT's) in the AlGaAs/GaAs material system can offer improved radiation response over commercially-available silicon bipolar junction transistors (BJT's). To be a viable alternative to the silicon Pnp BJT, improvements to the manufacturability of the HBT were required. Utilization of a Pd/Ge/Au non-spiking ohmic contact to the base and implementation of a PECVD silicon nitride hard mask for wet etch control were the primary developments that led to a more reliable fabrication process. The implementation of the silicon nitride hard mask and the subsequent process improvements increased the average electrical yield from 43% to 90%. © The Electrochemical Society.

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TYPE Conference YEAR 2007
ScopusOSTI
11 Results
11 Results