Publications

Patel, Rupal K.

Abstract not provided.

Serkland, Darwin K.; Childs, Kenton D.; Koudelka, Robert K.; Geib, K.M.; Klem, John F.; Hawkins, Samuel D.; Patel, Rupal K.

The key need that this project has addressed is a short-wave infrared light detector for ranging (LIDAR) imaging at temperatures greater than 100K, as desired by nonproliferation and work for other customers. Several novel device structures to improve avalanche photodiodes (APDs) were fabricated to achieve the desired APD performance. A primary challenge to achieving high sensitivity APDs at 1550 nm is that the small band-gap materials (e.g., InGaAs or Ge) necessary to detect low-energy photons exhibit higher dark counts and higher multiplication noise compared to materials like silicon. To overcome these historical problems APDs were designed and fabricated using separate absorption and multiplication (SAM) regions. The absorption regions used (InGaAs or Ge) to leverage these materials 1550 nm sensitivity. Geiger mode detection was chosen to circumvent gain noise issues in the III-V and Ge multiplication regions, while a novel Ge/Si device was built to examine the utility of transferring photoelectrons in a silicon multiplication region. Silicon is known to have very good analog and GM multiplication properties. The proposed devices represented a high-risk for high-reward approach. Therefore one primary goal of this work was to experimentally resolve uncertainty about the novel APD structures. This work specifically examined three different designs. An InGaAs/InAlAs Geiger mode (GM) structure was proposed for the superior multiplication properties of the InAlAs. The hypothesis to be tested in this structure was whether InAlAs really presented an advantage in GM. A Ge/Si SAM was proposed representing the best possible multiplication material (i.e., silicon), however, significant uncertainty existed about both the Ge material quality and the ability to transfer photoelectrons across the Ge/Si interface. Finally a third pure germanium GM structure was proposed because bulk germanium has been reported to have better dark count properties. However, significant uncertainty existed about the quantum efficiency at 1550 nm the necessary operating temperature. This project has resulted in several conclusions after fabrication and measurement of the proposed structures. We have successfully demonstrated the Ge/Si proof-of-concept in producing high analog gain in a silicon region while absorbing in a Ge region. This has included significant Ge processing infrastructure development at Sandia. However, sensitivity is limited at low temperatures due to high dark currents that we ascribe to tunneling. This leaves remaining uncertainty about whether this structure can achieve the desired performance with further development. GM detection in InGaAs/InAlAs, Ge/Si, Si and pure Ge devices fabricated at Sandia was shown to overcome gain noise challenges, which represents critical learning that will enable Sandia to respond to future single photon detection needs. However, challenges to the operation of these devices in GM remain. The InAlAs multiplication region was not found to be significantly superior to current InP regions for GM, however, improved multiplication region design of InGaAs/InP APDs has been highlighted. For Ge GM detectors it still remains unclear whether an optimal trade-off of parameters can achieve the necessary sensitivity at 1550 nm. To further examine these remaining questions, as well as other application spaces for these technologies, funding for an Intelligence Community post-doc was awarded this year.

Bennett, Reid S.; Patel, Rupal K.; Hsia, Alexander W.

Abstract not provided.

Bennett, Reid S.; Patel, Rupal K.; Hsia, Alexander W.

Abstract not provided.

Patel, Rupal K.; Hsia, Alexander W.; Bennett, Reid S.

A monolithic crystalline Si photovoltaic device, developing a potential of 2,120 Volts, has been demonstrated. The monolithic device consists of 3600 small photovoltaic cells connected in series and fabricated using standard CMOS processing on SOI wafers. The SOI wafers with trenches etched to the buried oxide (BOX) depth are used for cell isolation. The photovoltaic cell is a Si pn junction device with the n surface region forming the front surface diffused region upon which light impinges. Contact is formed to the deeper diffused region at the cell edge. The p+ deep-diffused region forms the contact to the p-type base region. Base regions were 5 or 10 {micro}m thick. Series connection of individual cells is accomplished using standard CMOS interconnects. This allows for the voltage to range from approximately 0.5 Volts for a single cell to above a thousand volts for strings of thousands of cells. The current is determined by cell area. The voltage is limited by dielectric breakdown. Each cell is isolated from the adjacent cells through dielectric-filled trench isolation, the substrate through the SOI buried oxide, and the metal wiring by the deposited pre-metal dielectric. If any of these dielectrics fail (whether due to high electric fields or inherent defects), the photovoltaic device will not produce the desired potential. We have used ultra-thick buried oxide SOI and several novel processes, including an oxynitride trench fill process, to avoid dielectric breakdown.

Patel, Rupal K.; Stein, David J.; Hsia, Alexander W.; Bennett, Reid S.

This report describes the features of monolithic, series connected silicon (Si) photovoltaic (PV) cells which have been developed for applications requiring higher voltages than obtained with conventional single junction solar cells. These devices are intended to play a significant role in micro / mini firing systems and fuzing systems for DOE and DOD applications. They are also appropriate for other applications (such as micro-electro-mechanical-systems (MEMS) actuation as demonstrated by Bellew et. al.) where electric power is required in remote regions and electrical connection to the region is unavailable or deemed detrimental for whatever reason. Our monolithic device consists of a large number of small PV cells, combined in series and fabricated using standard CMOS processing on silicon-on-insulator (SOI) wafers with 0.4 to 3 micron thick buried oxide (BOX) and top Si thickness of 5 and 10 microns. Individual cell isolation is achieved using the BOX layer of the SOI wafer on the bottom. Isolation along the sides is produced by trenching the top Si and subsequently filling the trench by deposition of dielectric films such as oxide, silicon nitride, or oxynitride. Multiple electrically isolated PV cells are connected in series to produce voltages ranging from approximately 0.5 volts for a single cell to several thousands of volts for strings of thousands of cells.