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ViArray standard platforms: Rad-hard structured ASICs for digital and mixed-signal applications

IEEE Aerospace Conference Proceedings

Teifel, John T.; Flores, Richard S.; Pearson, Sean P.; Begay, Cynthia B.; Ma, Kwok-Kee M.; Palmer, Jeremy A.

Sandia's radiation-hardened ViArray standard platforms use via-configurable circuits to create quick-turn, low-cost structured ASICs (Application Specific Integrated Circuits). Via-configurable technology enables performance similar to standard-cell ASICs, but with low-volume costs approaching that of programmable logic devices. Due to their significantly lower development cost and shorter production times, ViArray ASICs are rapidly replacing custom ASICs in Sandia's high-reliability digital and analog applications. This paper describes the Eiger ViArray platform, which is optimized for general-purpose digital applications, and the Whistler ViArray platform, which is optimized for mixed-signal instrumentation and state-of-health applications. 1 2 3 © 2012 IEEE.

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TYPE Conference YEAR 2012
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Effects of total dose irradiation on single-event upset hardness

IEEE Transactions on Nuclear Science

Schwank, James R.; Shaneyfelt, Marty R.; Felix, James A.; Dodd, Paul E.; Baggio, J.; Ferlet-Cavrois, V.; Paillet, P.; Hash, Gerald L.; Flores, Richard S.; Massengill, L.W.; Blackmore, E.

The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80°C after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents. © 2006 IEEE.

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TYPE Conference YEAR 2006
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Identification of radiation-induced parasitic leakage paths using light emission microscopy

IEEE Transactions on Nuclear Science

Shaneyfelt, Marty R.; Tangyunyong, Paiboon T.; Hill, Thomas A.; Soden, Jerry M.; Flores, Richard S.; Schwank, James R.; Dodd, Paul E.; Hash, Gerald L.

Eliminating radiation-induced parasitic leakage paths in integrated circuits (ICs) is key to improving their total dose hardness. Semiconductor manufacturers can use a combination of design and/or process techniques to eliminate known radiation-induced parasitic leakage paths. However, unknown or critical radiation-induced parasitic leakage may still exist on fully processed ICs and it is extremely difficult (if not impossible) to identify these leakage paths based on radiation induced parametric degradation. We show that light emission microscopy can be used to identify the location of radiation-induced parasitic leakage paths in ICs. This is illustrated by using light emission microscopy to find radiation-induced parasitic leakage paths in partially-depleted silicon on insulator static random-access memories (SRAMs). Once leakage paths were identified, modifications were made to the SRAM design to improve the total dose radiation hardness of the SRAMs. Light emission microscopy should prove to be an important tool for the development of future radiation hardened technologies and devices.

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TYPE Conference YEAR 2004
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22 Results