Publications

Electrostatic discharge (ESD) and electrical overstress (EOS) damage of Micro-Electro-Mechanical Systems (MEMS) has been identified as a new failure mode. This failure mode has not been previously recognized or addressed primarily due to the mechanical nature and functionality of these systems, as well as the physical failure signature that resembles stiction. Because many MEMS devices function by electrostatic actuation, the possibility of these devices not only being susceptible to ESD or EOS damage but also having a high probability of suffering catastrophic failure due to ESD or EOS is very real. Results from previous experiments have shown stationary comb fingers adhered to the ground plane on MEMS devices tested in shock, vibration, and benign environments. Using Sandia polysilicon microengines, we have conducted tests to establish and explain the ESD/EOS failure mechanism of MEMS devices. These devices were electronically and optically inspected prior to and after ESD and EOS testing. This paper will address the issues surrounding MEMS susceptibility to ESD and EOS damage as well as describe the experimental method and results found from ESD and EOS testing. The tests were conducted using conventional IC failure analysis and reliability assessment characterization tools. In this paper we will also present a thermal model to accurately depict the heat exchange between an electrostatic comb finger and the ground plane during an ESD event.

One of the most significant challenges for technology characterization and future analysis is to keep instrumentation and techniques in step with the development of technology itself. Not only are dimensions shrinking and new materials being employed, but the rate of change is increasing. According to the 1999 International Technology Roadmap for Semiconductors (ITRS) the number and difficulty of the technical challenges continue to increase as technology moves forward. It could be argued that technology cannot be developed without appropriate analytical technique, nevertheless while much effort is being directed at materials and processes, only a small proportion is being directed at analysis. Whereas previous versions of the Semiconductor Industry Association roadmap contained a small number of implicit references to characterization and analysis, the 1999 ITRS contains many explicit references. It is clear that characterization is now woven through the roadmap, and technology developers in all areas appreciate the fact that new instrumentation and techniques will be required to sustain the rate of development the semiconductor industry has seen in recent years. Late in 1999, a subcommittee of the Sematech Product Analysis Forum reviewed the ITRS and identified a top-ten list of challenges which the failure analysis community will face as present technologies are extended and future technologies are developed. This paper discusses the PAF top-ten list of challenges, which is based primarily on the Difficult Challenges tables from each ITRS working group. Eight of the top-ten are challenges of significant technical magnitude, only two could be considered non-technical in nature. Most of these challenges cut across several working group areas and could be considered common threads in the roadmap, ranging from fault simulation and modeling to imaging small features, from electrical defect isolation to reprocessing.