Publications

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Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor $I$-$V$ characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e., positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. The suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III-V/Si heterogeneously integrated electronics.

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Wafer-level step-stress experiments on high voltage Npn InGaP/GaAs HBTs are presented. A methodology utilizing brief, monotonically increasing stresses and periodic, interrupted parametric characterization is presented. The method and various examples of step-stressed HBTs illustrate the value of the technique for screening the reliability of HBT wafers. Degradation modes observed in these InGaP/GaAs HBTs closely correspond to a subset of those in other, longer types of reliability experiments and can be relevant in a reliability screen. A statistical sampling of HBT wafers reveals a consistently realized critical destructive limit over a very narrow power range, which indicates that thermal stress is the main cause of degradation. When stepped just shy of the destructive limit, electrical characteristics are capable of revealing gradual degradation. The end state of stressing typically involves shorting of both the base-emitter and base-collector junctions. Interrupted characterization revealed cases where baseemitter shorts preceded base-collector shorts and other cases where base-collector shorts occurred first. Examples of degradation include reductions in reverse breakdown voltage, increases in the offset voltage, and drops in current gain. These wafer-level stepstress techniques show promise for reducing the large time lag between wafer fabrication and useful reliability screening in HBTs.

The National Solar Thermal Test Facility at Sandia National Laboratories has a unique test capability called the Molten Salt Test Loop (MSTL) system. MSTL is a test capability that allows customers and researchers to test components in flowing, molten nitrate salt. The components tested can range from materials samples, to individual components such as flex hoses, ball joints, and valves, up to full solar collecting systems such as central receiver panels, parabolic troughs, or linear Fresnel systems. MSTL provides realistic conditions similar to a portion of a concentrating solar power facility. The facility currently uses 60/40 nitrate 'solar salt' and can circulate the salt at pressure up to 600psi, temperature to 585 C, and flow rate of 400-600GPM depending on temperature. The purpose of this document is to provide a basis for customers to evaluate the applicability to their testing needs, and to provide an outline of expectations for conducting testing on MSTL. The document can serve as the basis for testing agreements including Work for Others (WFO) and Cooperative Research and Development Agreements (CRADA). While this document provides the basis for these agreements and describes some of the requirements for testing using MSTL and on the site at Sandia, the document is not sufficient by itself as a test agreement. The document, however, does provide customers with a uniform set of information to begin the test planning process.

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We present the design, fabrication, and characterization of a pixelated, hyperspectral arrayed component for Focal Plane Array (FPA) integration in the Long-Wave IR. This device contains tens of pixels within a single super-pixel which is tiled across the extent of the FPA. Each spectral pixel maps to a single FPA pixel with a spectral FWHM of 200nm. With this arrayed approach, remote sensing data may be accumulated with a non-scanning, "snapshot" imaging system. This technology is flexible with respect to individual pixel center wavelength and to pixel position within the array. Moreover, the entire pixel area has a single wavelength response, not the integrated linear response of a graded cavity thickness design. These requirements bar tilted, linear array technologies where the cavity length monotonically increases across the device. © 2010 Copyright SPIE - The International Society for Optical Engineering.

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In this work, we describe the most recent progress towards the device modeling, fabrication, testing and system integration of active resonant subwavelength grating (RSG) devices. Passive RSG devices have been a subject of interest in subwavelength-structured surfaces (SWS) in recent years due to their narrow spectral response and high quality filtering performance. Modulating the bias voltage of interdigitated metal electrodes over an electrooptic thin film material enables the RSG components to act as actively tunable high-speed optical filters. The filter characteristics of the device can be engineered using the geometry of the device grating and underlying materials. Using electron beam lithography and specialized etch techniques, we have fabricated interdigitated metal electrodes on an insulating layer and BaTiO3 thin film on sapphire substrate. With bias voltages of up to 100V, spectral red shifts of several nanometers are measured, as well as significant changes in the reflected and transmitted signal intensities around the 1.55um wavelength. Due to their small size and lack of moving parts, these devices are attractive for high speed spectral sensing applications. We will discuss the most recent device testing results as well as comment on the system integration aspects of this project. © 2010 Copyright SPIE - The International Society for Optical Engineering.

This project demonstrates the feasibility of a novel imager with a thickness measured in microns rather than inches. Traditional imaging systems, i.e. cameras, cannot provide both the necessary resolution and innocuous form factor required in many data acquisition applications. Designing an imaging system with an extremely thin form factor (less than 1 mm) immediately presents several technical challenges. For instance, the thickness of the optical lens must be reduced drastically from currently available lenses. Additionally, the image circle is reduced by a factor equal to the reduction in focal length. This translates to fewer detector pixels across the image. To reduce the optical total track requires the use of specialized micro-optics and the required resolution necessitates the use of a new imaging modality. While a single thin imager will not produce the desired output, several thin imagers can be multiplexed and their low resolution (LR) outputs used together in post-processing to produce a high resolution (HR) image. The utility of an Iterative Back Projection (IBP) algorithm has been successfully demonstrated for performing the required post-processing. Advanced fabrication of a thin lens was also demonstrated and experimental results using this lens as well as commercially available lenses are presented.

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GaN-based microwave power amplifiers have been identified as critical components in Sandia's next generation micro-Synthetic-Aperture-Radar (SAR) operating at X-band and Ku-band (10-18 GHz). To miniaturize SAR, GaN-based amplifiers are necessary to replace bulky traveling wave tubes. Specifically, for micro-SAR development, highly reliable GaN high electron mobility transistors (HEMTs), which have delivered a factor of 10 times improvement in power performance compared to GaAs, need to be developed. Despite the great promise of GaN HEMTs, problems associated with nitride materials growth currently limit gain, linearity, power-added-efficiency, reproducibility, and reliability. These material quality issues are primarily due to heteroepitaxial growth of GaN on lattice mismatched substrates. Because SiC provides the best lattice match and thermal conductivity, SiC is currently the substrate of choice for GaN-based microwave amplifiers. Obviously for GaN-based HEMTs to fully realize their tremendous promise, several challenges related to GaN heteroepitaxy on SiC must be solved. For this LDRD, we conducted a concerted effort to resolve materials issues through in-depth research on GaN/AlGaN growth on SiC. Repeatable growth processes were developed which enabled basic studies of these device layers as well as full fabrication of microwave amplifiers. Detailed studies of the GaN and AlGaN growth of SiC were conducted and techniques to measure the structural and electrical properties of the layers were developed. Problems that limit device performance were investigated, including electron traps, dislocations, the quality of semi-insulating GaN, the GaN/AlGaN interface roughness, and surface pinning of the AlGaN gate. Surface charge was reduced by developing silicon nitride passivation. Constant feedback between material properties, physical understanding, and device performance enabled rapid progress which eventually led to the successful fabrication of state of the art HEMT transistors and amplifiers.

A comparison of the performance of WSi x rectifiers with Ni/SiC Schottky rectifiers to high dose γ-ray irradiation was discussed. SiC Schottky rectifiers with moderate breakdown voltages of ∼450 V and with either WSi x or Ni rectifying contacts were irradiated with Co-60 γ-rays. It was found that high dose γ-ray irradiation of N/SiC schottky rectifiers show significant degradation of the forward current characteristics, due to instability of the contacts. The results show that the WSi x/SiC rectifiers show little deterioration of the contact with the same conditions.

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The impressive performance improvements of laterally oxidized VCSELs come at the expense of increased fabrication complexity for 2-dimensional arrays. Since the epitaxial layers to be wet-thermally oxidized must be exposed, non-planarity can be an issue. This is particularly important in that electrical contact to both the anode and cathode of the diode must be brought out to a package. We have investigated four fabrication sequences suitable for the fabrication of 2-dimensional VCSEL arrays. These techniques include: mesa etched polymer planarized, mesa etched bridge contacted, mesa etched oxide isolated (where the electrical trace is isolated from the substrate during the oxidation) and oxide/implant isolation (oxidation through small via holes) all of which result in VCSELs with outstanding performance. The suitability of these processes for manufacturing are assessed relative to oxidation uniformity, device capacitance, and structural ruggedness for packaging.

Vertical cavity surface emitting lasers (VCSELs) which operate in multiple transverse optical modes have been rapidly adopted into present data communication applications which rely on multi-mode optical fiber. However, operation only in the fundamental mode is required for free space interconnects and numerous other emerging VCSEL applications. Two device design strategies for obtaining single mode lasing in VCSELs based on mode selective loss or mode selective gain are reviewed and compared. Mode discrimination is attained with the use of a thick tapered oxide aperture positioned at a longitudinal field null. Mode selective gain is achieved by defining a gain aperture within the VCSEL active region to preferentially support the fundamental mode. VCSELs which exhibit greater than 3 mW of single mode output power at 850 nm with mode suppression ratio greater than 30 dB are reported.