Passive silicon photonic waveguides are exposed to gamma radiation to understand how the performance of silicon photonic integrated circuits is affected in harsh environments such as space or high energy physics experiments. The propagation loss and group index of the mode guided by these waveguides is characterized by implementing a phase sensitive swept-wavelength interferometric method. We find that the propagation loss associated with each waveguide geometry explored in this study slightly increases at absorbed doses of up to 100 krad (Si). The measured change in group index associated with the same waveguide geometries is negligibly changed after exposure. Additionally, we show that the post-exposure degradation of these waveguides can be improved through heat treatment.
Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories' CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
The effect of a linear accelerator's (LINAC's) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.
Dodds, N.A.; Martinez, Marino M.; Dodd, Paul E.; Shaneyfelt, Marty R.; Sexton, Frederick W.; Black, J.D.; Lee, David S.; Swanson, Scot E.; Bhuva, B.L.; Warren, K.M.; Reed, R.A.; Trippe, J.; Sierawski, B.D.; Weller, R.A.; Mahatme, N.; Gaspard, N.J.; Assis, T.; Austin, R.; Weeden-Wright, S.L.; Massengill, L.W.; Swift, G.; Wirthlin, M.; Cannon, M.; Liu, R.; Chen, L.; Kelly, A.T.; Marshall, P.W.; Trinczek, M.; Blackmore, E.W.; Wen, S.J.; Wong, R.; Narasimham, B.; Pellish, J.A.; Puchner, H.
Low-and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
We present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.
In this study, we present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.
Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled "Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam." For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).
The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. We show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.
The locations of conductive regions in TaOx memristors are spatially mapped using a microbeam and Nanoimplanter by rastering an ion beam across each device while monitoring its resistance. Microbeam irradiation with 800 keV Si ions revealed multiple sensitive regions along the edges of the bottom electrode. The rest of the active device area was found to be insensitive to the ion beam. Nanoimplanter irradiation with 200 keV Si ions demonstrated the ability to more accurately map the size of a sensitive area with a beam spot size of 40 nm by 40 nm. Isolated single spot sensitive regions and a larger sensitive region that extends approximately 300 nm were observed.