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Hybrid MEMS-CMOS ion traps for NISQ computing

Quantum Science and Technology

Blain, Matthew G.; Haltli, Raymond A.; Maunz, P.; Nordquist, C.D.; Revelle, Melissa R.; Stick, D.

Surging interest in engineering quantum computers has stimulated significant and focused research on technologies needed to make them manufacturable and scalable. In the ion trap realm this has led to a transition from bulk three-dimensional macro-scale traps to chip-based ion traps and included important demonstrations of passive and active electronics, waveguides, detectors, and other integrated components. At the same time as these technologies are being developed the system sizes are demanding more ions to run noisy intermediate scale quantum (NISQ) algorithms, growing from around ten ions today to potentially a hundred or more in the near future. To realize the size and features needed for this growth, the geometric and material design space of microfabricated ion traps must expand. In this paper we describe present limitations and the approaches needed to overcome them, including how geometric complexity drives the number of metal levels, why routing congestion affects the size and location of shunting capacitors, and how RF power dissipation can limit the size of the trap array. We also give recommendations for future research needed to accommodate the demands of NISQ scale ion traps that are integrated with additional technologies.

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TYPE Journal Article YEAR 2021
ScopusOSTIDOI

TICTOC: Compact Atomic Clock with Integrated Photonics

Ivory, Megan K.; Ivory, Megan K.; Gehl, M.; Gehl, M.; Setzer, William J.; Setzer, William J.; McGuinness, Hayden J.; McGuinness, Hayden J.; Haltli, Raymond A.; Haltli, Raymond A.; Blain, Matthew G.; Blain, Matthew G.; Stick, Daniel L.; Stick, Daniel L.; Parazzoli, Lambert P.; Parazzoli, Lambert P.

Atomic clocks are precision timekeeping devices that form the basis for modern communication and navigation. While many atomic clocks are room-sized systems requiring bulky free space optics and detectors, the Trapped-lon Clock using Technology-On-Chip (TICTOC) project integrates these components into Sandia's existing surface trap technology via waveguides for beam delivery and avalanche photodiodes for light detection. Taking advantage of a multi-ensemble clock interrogation approach, we expect to achieve record time stability (< 1 ns error per year) in a compact (< /1 2 L) clock. Here, we present progress on the development of the integrated devices and recent trapped ion demonstrations.

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TYPE Conference Poster YEAR 2019
OSTI

Galvanostatic plating with a single additive electrolyte for bottom-up filling of copper in mesoscale TSVs

Journal of the Electrochemical Society

Menk, L.A.; Baca, Ehren B.; Blain, Matthew G.; McClain, Jaime L.; Dominguez, Jason J.; Smith, A.; Hollowell, Andrew E.

A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.

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TYPE Journal Article YEAR 2019
ScopusOSTIDOI
Results 1–25 of 84
Results 1–25 of 84