Copper Electrodeposition in Through Sillicon Vias: Scaling from Die Level to Wafer Level Plating
Abstract not provided.
Publications
Void-free copper electrodeposition in high aspect ratio, full wafer thickness through-silicon vias with endpoint detection
Journal of the Electrochemical Society
High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μm diameter TSVs, etched into a 625 μm thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO4-H2SO4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.
Cu ECD in High Aspect Ratio Mesoscale TSVs: Scaling from Die Level to Wafer Level Plating
Abstract not provided.
Copper Electrodeposition in High Aspect Ratio Mesoscale Through-Silicon Vias: Scaling from Die Level to Wafer Level Plating
Abstract not provided.
Tutorial on forming through-silicon vias
Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.
Heterogeneous Integration of 3D Photonic Integrated Circuits
Abstract not provided.
Void-Free Copper Electrodeposition in Full Wafer Thickness Through-Silicon Vias (TSVs)
Abstract not provided.
Development of a Scalable Two-Additive Electrodeposition System for Bottom-Up Copper Filling of Sub-Millimeter Through Silicon Vias
Abstract not provided.
High aspect ratio silicon template fabrication for 100 keV X-ray phase contrast imaging
Abstract not provided.
On Gas Ingression of Hermetic Packages
IEEE Transactions on Components, Packaging and Manufacturing Technology
In this paper, a closed-form mathematic equation that governs gas ingression of hermetic packages is derived from first principles and applied to moist air and water vapor ingression conditions. The equation models internal gas partial pressure change as a function of time, external conditions, and package characteristics. The equation provides the theoretical basis for direct comparisons of ingression behaviors of different gases into hermetic packages. Comparing the rates of internal air pressure increase due to air ingression and water vapor partial pressure buildup due to water vapor ingression, the authors theorize that vacuum decay may present a greater challenge to the performance of microelectromechanical systems (MEMS) devices within hermetic packages than that of water vapor content induced corrosion failures. This paper also examines gas ingression of hermetic enclosures with multiple layers of seals.
Fabrication of extreemly high aspect ratio diffraction gratings for X-ray phase contrast imaging
Abstract not provided.
Copper Electrodeposition in Mesoscale Through-Silicon-Vias
Abstract not provided.
Copper Electrodeposition in Mesoscale Through-Silicon-Vias
Abstract not provided.
Copper Electrodeposition in Mesoscale Through-Silicon-Vias
Abstract not provided.
Copper Electrodeposition in Mesoscale Through-Silicon-Vias
Abstract not provided.
Utilizing Electroplating for High Aspect Ratio Mesoscale Fabrication - Filling Forming and Coating
Abstract not provided.
ALD Platinum Surface Preparation and Copper Electrodeposition in Blind Mesoscale Through-Silicon-Vias
Abstract not provided.
A Unique 3D Integration Approach for SOI Substrates
Abstract not provided.
Optimization of Electrochemical Deposition of Gold
Abstract not provided.
19 Results