Structural modularity is critical to solid-state transformer (SST) and solid-state power substation (SSPS) concepts, but operational aspects related to this modularity are not yet fully understood. Previous studies and demonstrations of modular power conversion systems assume identical module compositions, but dependence on module uniformity undercuts the value of the modular framework. In this project, a hierarchical control approach was developed for modular SSTs which achieves system-level objectives while ensuring equitable power sharing between nonuniform building block modules. This enables module replacements and upgrades which leverage circuit and device technology advancements to improve system-level performance. The functionality of the control approach is demonstrated in detailed time-domain simulations. Results of this project provide context and strategic direction for future LDRD projects focusing on technologies supporting the SST crosscut outcome of the resilient energy systems mission campaign.
A new three-level isolated ac-dc power factor correction (PFC) topology with a minimum number of semiconductor devices is the focus of this article. This topology provides a high input power factor (PF), soft-switching, and higher efficiency than existing isolated ac-dc converters. Furthermore, the proposed circuit has lower voltage rating requirements for the secondary side devices, which leads to a lower total cost and minimizes total converter losses. This article presents a theoretical analysis describing the complete characterization of this new topology, and experimental results on a 1-kW prototype showing high PF and efficiency throughout the operating range.
Deep level defects in wide bandgap semiconductors, whose response times are in the range of power converter switching times, can have a significant effect on converter efficiency. Here, we use deep level transient spectroscopy (DLTS) to evaluate such defect levels in the n-drift layer of vertical gallium nitride (v-GaN) power diodes with VBD ~ 1500 V. DLTS reveals three energy levels that are at ~0.6 eV (highest density), ~0.27 eV (lowest density), and ~45 meV (a dopant level) from the conduction band. Dopant extraction from capacitance–voltage measurement tests (C–V) at multiple temperatures enables trap density evaluation, and the ~0.6 eV trap has a density of 1.2 × 1015 cm-3. The 0.6 eV energy level and its density are similar to a defect that is known to cause current collapse in GaN based surface conducting devices (like high electron mobility transistors). Analysis of reverse bias currents over temperature in the v-GaN diodes indicates a predominant role of the same defect in determining reverse leakage current at high temperatures, reducing switching efficiency.
This paper presents a new high gain, multilevel, bidirectional DC-DC converter for interfacing battery energy storage systems (BESS) with the distribution grid. The proposed topology employs a current-fed structure on the low-voltage (LV) BESS side to obtain high voltage gain during battery-to-grid mode of operation without requiring a large turns ratio isolation transformer. The high-voltage (HV) side of the converter is a voltage-doubler network comprising two half-bridge circuits with an intermediary bidirectional switch that re-configures the two bridges in series connection to enhance the boost ratio. A seamless commutation of the transformer leakage inductor current is ensured by the phase-shift modulation of HV side devices. The modulating duty cycle of the intermediary bidirectional devices generates a multilevel voltage of twice the switching frequency at the grid-side dc link, which significantly reduces the filter size. The presented modulation strategy ensures zero current switching (ZCS) of the LV devices and zero voltage switching (ZVS) of the HV devices to achieve a high power conversion efficiency. Design and operation of the proposed converter is explained with modal analysis, and further verified by detailed simulation results.
With evolving landscape of DC power transmission and distribution, a reliable and fast protection against faults is critical, especially for medium- and high-voltage applications. Thus, solid-state circuit breakers (SSCB), consisting of cascaded silicon carbide (SiC) junction field-effect transistors (JFET), utilize the intrinsic normally-ON characteristic along with their low ON-resistance. This approach provides an efficient and robust protection solution from detrimental short-circuit events. However, for applications that require high-voltage blocking capability, a proper number of JFETs need be connected in series to achieve the desired blocking voltage rating. Ensuring equal voltage balancing across the JFETs during the switching transitions as well as the blocking stage is critical and hence, this paper presents a novel passive balancing network for series connected JFETs for DC SSCB applications. The dynamic voltage balancing network to synchronize both the turn ON and OFF intervals is described analytically. Moreover, the static voltage balancing network is implemented to establish equal sharing of the total blocking voltage across the series connection of JFETs. The proposed dynamic and steady-state balancing networks are validated by SPICE simulation and experimental results.
In spite of several advantages of SiC JFETs over enhancement mode SiC MOSFETs, the intrinsic normally-ON characteristic of the JFETs can be undesirable for many industrial power conversion applications due to the negative turn-OFF voltage requirement. This prevents normally-ON JFETs from being widely accepted in industry. However, a cascode configuration, which uses a low voltage (LV) Si MOSFET can be used to enable a normally-OFF behavior, making this approach an attractive solution to utilize the benefits of SiC JFETs. For medium-, and high-voltage applications that require larger blocking voltage than the rating of each JFET, additional devices can be connected in series to increase the overall blocking voltage capability, creating a super-cascode configuration. This paper provides a review of several super-cascode topology variations and presents a comprehensive comparative study, evaluating similarities and differences in operating principles, equivalent circuits, and design considerations and limitations.
This paper presents an isolated bidirectional dc/dc converter for battery energy storage applications. Two main features of the proposed circuit topology are high voltage-conversion ratio and reduced battery current ripple. The primary side circuit is a quasi-switched-capacitor circuit with reduced voltage stress on switching devices and a 3:1 voltage step down ratio, which reduces the turns ratio of the transformer to 6:1:1. The secondary side circuit has an interleaved operation by utilizing the split magnetizing inductance of the transformer, which not only helps to increase the step down ratio but also reduces the battery current ripple. Similar to the dual-active-bridge circuit, the phase shift control is implemented to regulate the operation power of the circuit. A 1-kW, 300-kHz, 380-420 V/20-33 V GaN-based circuit prototype is currently under fabrication. The preliminary test results are presented.