Single Event Effects Testing Results in Sandia National Laboratories Via Programmable ASIC Platforms
Abstract not provided.
Publications
ViArray standard platforms: Rad-hard structured ASICs for digital and mixed-signal applications
IEEE Aerospace Conference Proceedings
Sandia's radiation-hardened ViArray standard platforms use via-configurable circuits to create quick-turn, low-cost structured ASICs (Application Specific Integrated Circuits). Via-configurable technology enables performance similar to standard-cell ASICs, but with low-volume costs approaching that of programmable logic devices. Due to their significantly lower development cost and shorter production times, ViArray ASICs are rapidly replacing custom ASICs in Sandia's high-reliability digital and analog applications. This paper describes the Eiger ViArray platform, which is optimized for general-purpose digital applications, and the Whistler ViArray platform, which is optimized for mixed-signal instrumentation and state-of-health applications. 1 2 3 © 2012 IEEE.
Moore's law and the impact on trusted and radiation-hardened microelectronics
In 1965 Gordon Moore wrote an article claiming that integrated circuit density would scale exponentially. His prediction has remained valid for more than four decades. Integrated circuits have changed all aspects of everyday life. They are also the 'heart and soul' of modern systems for defense, national infrastructure, and intelligence applications. The United States government needs an assured and trusted microelectronics supply for military systems. However, migration of microelectronics design and manufacturing from the United States to other countries in recent years has placed the supply of trusted microelectronics in jeopardy. Prevailing wisdom dictates that it is necessary to use microelectronics fabricated in a state-of-the-art technology for highest performance and military system superiority. Close examination of silicon microelectronics technology evolution and Moore's Law reveals that this prevailing wisdom is not necessarily true. This presents the US government the possibility of a totally new approach to acquire trusted microelectronics.
ViArray Standard Platforms: Rad-hard structured ASICs for Digital and Mixed-signal Applications
Abstract not provided.
Sandia rad-hard, fast turn structured ASIC :
Abstract not provided.
Sandia Rad-Hard Fast-Turn Structured ASIC - The ViArray
Abstract not provided.
ViArray Standard Platforms: Rad-Hard Structured ASICs for Digital and Mixed-Signal Applications
Abstract not provided.
What's Beyond Moore's Law?
Abstract not provided.
Asynchronous logic design for rad-hard structure ASICs
Abstract not provided.
Asynchronous logic design for rad-hard structrued ASICs
Abstract not provided.
Sandia national Laboratories microelectronics program
Abstract not provided.
Sandia National Laboratories Microelectronics Program
Abstract not provided.
Sandia secure processor : a native Java processor
The Sandia Secure Processor (SSP) is a new native Java processor that has been specifically designed for embedded applications. The SSP's design is a system composed of a core Java processor that directly executes Java bytecodes, on-chip intelligent IO modules, and a suite of software tools for simulation and compiling executable binary files. The SSP is unique in that it provides a way to control real-time IO modules for embedded applications. The system software for the SSP is a 'class loader' that takes Java .class files (created with your favorite Java compiler), links them together, and compiles a binary. The complete SSP system provides very powerful functionality with very light hardware requirements with the potential to be used in a wide variety of small-system embedded applications. This paper gives a detail description of the Sandia Secure Processor and its unique features.
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