Publications

Proceedings of SPIE - The International Society for Optical Engineering

Orendorff, Christopher O.; Barker, Joy M.; Rowen, Adam M.; Yelton, W.G.; Arrington, Christian L.; Gillen, J.R.

Higher performance is the main driver in the integrated circuit (IC) market, but along with added function comes the cost of increased input/output connections and larger die sizes. Space saving approaches aimed at solving these challenges includes two technologies; 3D stacking (3D-ICs) and flip chip assemblies. Emerging ICs require sub-micron scale interconnects which include vias for 3D-ICs and bump bonds for flip chips. Photolithographic techniques are commonly used to prepare templates followed by metal vapor deposition to create flip chip bump bonds. Both the lithography step and the metal properties required for bump bonding contribute to limiting this approach to a minimum bump size of ∼10 μm. Here, we present a wet chemistry approach to fabricating uniform bump bonds of tunable size and height down to the nanoscale. Nanosphere lithography (NSL), a "soft" lithographic technique, is used to create a bump bond template or mask for nanoscale bumps. Electrochemical deposition is also used through photoresist templates to create uniform bump bonds across large area wafers or dies. This template approach affords bumps with tunable diameters from 100s of nanometers to microns (allowing for tunable interconnect pitch and via diameters) while the use of constant current electoplating gives uniform bump height over large areas (>1 cm2).