Wafer-Level Step-Stressing of InGaP/GaAs HBTs
ECS Transactions
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Wafer-level step-stressing of InGaP/GaAs HBTs
ECS Transactions
Wafer-level step-stress experiments on high voltage Npn InGaP/GaAs HBTs are presented. A methodology utilizing brief, monotonically increasing stresses and periodic, interrupted parametric characterization is presented. The method and various examples of step-stressed HBTs illustrate the value of the technique for screening the reliability of HBT wafers. Degradation modes observed in these InGaP/GaAs HBTs closely correspond to a subset of those in other, longer types of reliability experiments and can be relevant in a reliability screen. A statistical sampling of HBT wafers reveals a consistently realized critical destructive limit over a very narrow power range, which indicates that thermal stress is the main cause of degradation. When stepped just shy of the destructive limit, electrical characteristics are capable of revealing gradual degradation. The end state of stressing typically involves shorting of both the base-emitter and base-collector junctions. Interrupted characterization revealed cases where baseemitter shorts preceded base-collector shorts and other cases where base-collector shorts occurred first. Examples of degradation include reductions in reverse breakdown voltage, increases in the offset voltage, and drops in current gain. These wafer-level stepstress techniques show promise for reducing the large time lag between wafer fabrication and useful reliability screening in HBTs.
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