In this study we examine a split-foundry multilevel application specific integrated circuit (ASIC) Si-interposer and die bonded using the direct bond interface (DBI) process, in addition to shortloop vehicles. The designs have been subject to relaxed pattern density rules, and exhibit chemical mechanical planarization (CMP) systematic process issues of varying degrees. We find that the interconnect formation is robust against moderate dielectric thickness variation, as well as a moderate degree of copper corrosion. We discuss and demonstrate various CMP methods which have a clear and repeatable impact. Pattern density effects and defectivity on the bond quality are examined using focused ion beam scanning electron microscope (FIB-SEM) images at the feature scale (sub 100 um) and intra-die scale (few mm). Impact to the CMP performance, including plug recess, and defectivity are discussed.
We report on the fabrication and characterization of Nb/Ta-N/Nb Josephson junctions grown by room temperature magnetron sputtering on 150-mm diameter Si wafers. Junction characteristics depend upon the Ta-N barrier composition, which was varied by adjusting the N2 flow during film deposition. Higher N2 flow rates raise the barrier resistance and increase the junction critical current. This work demonstrates the viability of Ta-N as an alternative barrier to aluminum oxide, with the potential for large scale integration.
Direct bond interconnect (DBI) processes enable chip to chip, low resistivity electrical connections for 2.5-D scaling of electrical circuits and heterogenous integration. This work describes SiO2/Cu DBI technology with Cu interconnect performance investigated over a range of inter-die Cu gap heights and post-bond annealing temperatures. Chemical mechanical polishing (CMP) generates wafers with a controlled Cu recess relative to the SiO2 surface, yielding die pairs with inter-die Cu gap heights ranging between 9 and 47 nm. Bonded die with different gap heights show similar per-connection resistance after annealing at 400 degrees Celsius but annealing at lower temperatures between 250 and 350 degrees Celsius results in failing or high-resistance interconnects with intermediate gaps showing lowest resistance. Cross-section scanning electron microscope (SEM) image analysis shows that the microstructure is largely independent of post-bond annealing temperature, suggesting that the temperature behavior is due to nanoscale scale interfacial effects not observable by SEM. The bond strength is affirmed by successful step-wise mechanical and chemical removal of the handle silicon layer to reveal metal from both die. This work demonstrates a 2.5-D integration method using a 3 micron Cu DBI process on a 7.5 micron pitch with electrical contacts ranging between 3.8 and 4.8 Ohms per contact plug.