Sort by Date
Sort by Title
Standard Format
Show Abstracts
As Citations (APA)
Skip to search filters
IEEE Transactions on Nuclear Science
Black, Jeffrey B. ; Dame, Jeff A.; Black, Dolores A. ; Dodd, Paul E. ; Shaneyfelt, Marty R. ; Teifel, John T. ; Salas, Joseph G. ; Steinbach, Robert; Davis, Matthew; Reed, Robert A.; Weller, Robert A.; Trippe, James M. ; Warren, Kevin M.; Tonigan, Andrew M.; Schrimpf, Ronald D.; Marquez, Richard S.
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
Black, Jeffrey B. ; Dame, Jeff A.; Black, Dolores A. ; Dodd, Paul E. ; Shaneyfelt, Marty R. ; Teifel, John T. ; Salas, Joseph G. ; Steinbach, Robert S.; Davis, Matthew M.; Reed, Robert R.; Weller, Robert W.; Trippe, James M. ; Warren, Kevin W.; Tonigan, Andrew M.; Schrimpf, Ronald D.; Marquez, Richard S.
Abstract not provided.
Teifel, John T. ; Wang, Cheng C.; Teifel, John T.
Abstract not provided.
Teifel, John T. ; Wang, Cheng C.; Teifel, John T.
Abstract not provided.
Teifel, John T. ; Black, Jeffrey B. ; Cavanaugh, William S. ; clark, kevin c.; McCasland, Jeffrey T. ; Owen, Richard E. ; Sharif, Moslema S.
Abstract not provided.
Teifel, John T.
Abstract not provided.
Teifel, John T. ; Black, Jeffrey B. ; Cavanaugh, William S. ; Clark, Kevin D. ; McCasland, Jeffrey T. ; Owen, Richard E. ; Sharif, Moslema S.
Abstract not provided.
Teifel, John T. ; Land, Matthew L. ; Miller, Russell D.
Abstract not provided.
Teifel, John T. ; Land, Matthew L. ; Miller, Russell D.
Abstract not provided.
Black, Jeffrey B. ; Dodds, Nathaniel A. ; Dodd, Paul E. ; Shaneyfelt, Marty R. ; Martinez, Marino M. ; Teifel, John T. ; Pearson, Sean P. ; Ma, Kwok-Kee M.
Abstract not provided.
Teifel, John T. ; Black, Jeffrey B. ; Edwards, Eric E. ; Mannos, Tom M.
Abstract not provided.
Teifel, John T. ; Black, Jeffrey B. ; Edwards, Eric E. ; Mannos, Tom M.
Abstract not provided.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Nowlin, Robert N. ; Black, Jeffrey B.
Abstract not provided.
Teifel, John T. ; Flores, Richard S. ; Jarecki, Robert L. ; Bauer, Todd B. ; Shinde, Subhash L.
Abstract not provided.
Teifel, John T. ; Flores, Richard S. ; Jarecki, Robert L. ; Bauer, Todd B. ; Shinde, Subhash L.
Abstract not provided.
IEEE Aerospace Conference Proceedings
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Begay, Cynthia B. ; Ma, Kwok-Kee M. ; Palmer, Jeremy A.
Sandia's radiation-hardened ViArray standard platforms use via-configurable circuits to create quick-turn, low-cost structured ASICs (Application Specific Integrated Circuits). Via-configurable technology enables performance similar to standard-cell ASICs, but with low-volume costs approaching that of programmable logic devices. Due to their significantly lower development cost and shorter production times, ViArray ASICs are rapidly replacing custom ASICs in Sandia's high-reliability digital and analog applications. This paper describes the Eiger ViArray platform, which is optimized for general-purpose digital applications, and the Whistler ViArray platform, which is optimized for mixed-signal instrumentation and state-of-health applications. 1 2 3 © 2012 IEEE.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Begay, Cynthia B. ; Palmer, Jeremy A.
Abstract not provided.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Begay, Cynthia B. ; Ma, Kwok-Kee M. ; Palmer, Jeremy A.
Abstract not provided.
Ma, Kwok-Kee M. ; Teifel, John T. ; Flores, Richard S.
Abstract not provided.
Ma, Kwok-Kee M. ; Teifel, John T. ; Flores, Richard S.
Abstract not provided.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Begay, Cynthia B. ; Ma, Kwok-Kee M.
Abstract not provided.
IEEE Transactions on Nuclear Science
Teifel, John T.
Dual-modular-redundancy (DMR) architectures use duplication and self-voting asynchronous circuits to mitigate single event transients (SETs). The area and performance of DMR circuitry is evaluated against conventional triple-modular-redundancy (TMR) logic. Benchmark ASIC circuits designed with DMR logic show a 1024% area improvement for flip-flop designs, and a 33% improvement for latch designs. © 2006 IEEE.
IEEE Transactions on Nuclear Science
Teifel, John T.
Abstract not provided.
Teifel, John T.
Abstract not provided.
Teifel, John T.
Abstract not provided.
Results 1–25 of 28
25 Results per page
50 Results per page
100 Results per page
200 Results per page