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Using MRED to Screen Multiple-Node Charge-Collection Mitigated SOI Layouts

IEEE Transactions on Nuclear Science

Black, Jeffrey B.; Dame, Jeff A.; Black, Dolores A.; Dodd, Paul E.; Shaneyfelt, Marty R.; Teifel, John T.; Salas, Joseph G.; Steinbach, Robert; Davis, Matthew; Reed, Robert A.; Weller, Robert A.; Trippe, James M.; Warren, Kevin M.; Tonigan, Andrew M.; Schrimpf, Ronald D.; Marquez, Richard S.

Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.

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TYPE Conference Poster YEAR 2019
ScopusOSTIDOI

ViArray standard platforms: Rad-hard structured ASICs for digital and mixed-signal applications

IEEE Aerospace Conference Proceedings

Teifel, John T.; Flores, Richard S.; Pearson, Sean P.; Begay, Cynthia B.; Ma, Kwok-Kee M.; Palmer, Jeremy A.

Sandia's radiation-hardened ViArray standard platforms use via-configurable circuits to create quick-turn, low-cost structured ASICs (Application Specific Integrated Circuits). Via-configurable technology enables performance similar to standard-cell ASICs, but with low-volume costs approaching that of programmable logic devices. Due to their significantly lower development cost and shorter production times, ViArray ASICs are rapidly replacing custom ASICs in Sandia's high-reliability digital and analog applications. This paper describes the Eiger ViArray platform, which is optimized for general-purpose digital applications, and the Whistler ViArray platform, which is optimized for mixed-signal instrumentation and state-of-health applications. 1 2 3 © 2012 IEEE.

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TYPE Conference YEAR 2012
ScopusOSTI

Self-voting dual-modular-redundancy circuits for single-event-transient mitigation

IEEE Transactions on Nuclear Science

Teifel, John T.

Dual-modular-redundancy (DMR) architectures use duplication and self-voting asynchronous circuits to mitigate single event transients (SETs). The area and performance of DMR circuitry is evaluated against conventional triple-modular-redundancy (TMR) logic. Benchmark ASIC circuits designed with DMR logic show a 1024% area improvement for flip-flop designs, and a 33% improvement for latch designs. © 2006 IEEE.

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TYPE Conference YEAR 2008
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Results 1–25 of 28