We demonstrate the generation of a cold-atom ensemble within a sub-millimeter diameter hole in a transparent membrane, a so-called “membrane MOT”. With a sub-Doppler cooling process, the atoms trapped by the membrane MOT are cooled down to 10 μ K. The atom number inside the unbridged/bridged membrane hole is about 10 4 to 10 5, and the 1 / e2-diameter of the MOT cloud is about 180 μ m for a 400 μ m-diameter membrane hole. Such a membrane device can, in principle, efficiently load cold atoms into the evanescent-field optical trap generated by the suspended membrane waveguide for strong atom-light interaction and provide the capability of sufficient heat dissipation at the waveguide. This represents a key step toward the photonic atom trap integrated platform (ATIP).
We report experimental and numerical developments extending the operating range of vanadium dioxide based optical limiters into the short-wavelength infrared. Pixelated sensor elements have been fabricated which show optically-triggered limiting of a 2.7 µm probe.
We present an implementation that can keep a coldatom ensemble within a sub-millimeter diameter hole in a transparent membrane. Based on the effective beam diameter of the magneto-optical trap (MOT), d = 400 mm-hole diameter, we measure the atom number that is 105 times higher than the predicted value using the conventional d6 scaling rule. Atoms trapped by the membrane MOT are cooled down to 10 mK with sub- Doppler cooling process and can be potentially coupled to the photonic/electronic integrated circuits that can be fabricated in the membrane device by taking a step toward the atom trap integrated platform.
In this study we examine a split-foundry multilevel application specific integrated circuit (ASIC) Si-interposer and die bonded using the direct bond interface (DBI) process, in addition to shortloop vehicles. The designs have been subject to relaxed pattern density rules, and exhibit chemical mechanical planarization (CMP) systematic process issues of varying degrees. We find that the interconnect formation is robust against moderate dielectric thickness variation, as well as a moderate degree of copper corrosion. We discuss and demonstrate various CMP methods which have a clear and repeatable impact. Pattern density effects and defectivity on the bond quality are examined using focused ion beam scanning electron microscope (FIB-SEM) images at the feature scale (sub 100 um) and intra-die scale (few mm). Impact to the CMP performance, including plug recess, and defectivity are discussed.
Direct bond interconnect (DBI) processes enable chip to chip, low resistivity electrical connections for 2.5-D scaling of electrical circuits and heterogenous integration. This work describes SiO2/Cu DBI technology with Cu interconnect performance investigated over a range of inter-die Cu gap heights and post-bond annealing temperatures. Chemical mechanical polishing (CMP) generates wafers with a controlled Cu recess relative to the SiO2 surface, yielding die pairs with inter-die Cu gap heights ranging between 9 and 47 nm. Bonded die with different gap heights show similar per-connection resistance after annealing at 400 degrees Celsius but annealing at lower temperatures between 250 and 350 degrees Celsius results in failing or high-resistance interconnects with intermediate gaps showing lowest resistance. Cross-section scanning electron microscope (SEM) image analysis shows that the microstructure is largely independent of post-bond annealing temperature, suggesting that the temperature behavior is due to nanoscale scale interfacial effects not observable by SEM. The bond strength is affirmed by successful step-wise mechanical and chemical removal of the handle silicon layer to reveal metal from both die. This work demonstrates a 2.5-D integration method using a 3 micron Cu DBI process on a 7.5 micron pitch with electrical contacts ranging between 3.8 and 4.8 Ohms per contact plug.
The thickening behavior of aluminum scandium nitride (Al0.88Sc0.12N) films grown on Si(111) substrates has been investigated experimentally using X-ray diffraction (XRD), transmission electron microscopy (TEM), atomic force microscopy, and residual stress measurement. Al0.88Sc0.12N films were grown with thicknesses spanning 14 nm to 1.1 um. TEM analysis shows that the argon sputter etch used to remove the native oxide prior to deposition produced an amorphous, oxygen-rich surface, preventing epitaxial growth. XRD analysis of the films show that the A1ScN(002) orientation improves as the films thicken and the XRD A1ScN(002) rocking curve full width half maximum decreases to 1.34 q for the 1.1 pm thick film. XRD analysis shows that the unit cell is expanded in both the a- and c-axes by Sc doping; the a-axis lattice parameter was measured to be 3.172 ± 0.007 A and the c-axis lattice parameter was measured to be 5.000 ± 0.001 A, representing 1.96% and 0.44% expansions over aluminum nitride lattice parameters, respectively. The grain size and roughness increase as the film thickness increases. A stress gradient forms through the film; the residual stress grows more tensile as the film thickens, from -1.24 GPa to +8.5MPa.
Properties of NbN and TaxN thin films grown at ambient temperatures on SiO2/Si substrates by reactive-pulsed laser deposition and reactive magnetron sputtering (MS) as a function of N2 gas flow were investigated. Both techniques produced films with smooth surfaces, where the surface roughness did not depend on the N2 gas flow during growth. High crystalline quality, (111) oriented NbN films with Tc up to 11 K were produced by both techniques for N contents near 50%. The low temperature transport properties of the TaxN films depended upon both the N2 partial pressure used during growth and the film thickness. The root mean square surface roughness of TaxN films grown by MS increased as the film thickness decreased down to 10 nm.
The last two decades have seen an explosion in worldwide R&D, enabling fundamentally new capabilities while at the same time changing the international technology landscape. The advent of technologies for continued miniaturization and electronics feature size reduction, and for architectural innovations, will have many technical, economic, and national security implications. It is important to anticipate possible microelectronics development directions and their implications on US national interests. This report forecasts and assesses trends and directions for several potentially disruptive microfabrication capabilities and device architectures that may emerge in the next 5-10 years.