The Spiking/Processing Array (spARR) is a novel photonic focal plane that uses pixels which generate electronic spikes autonomously and without a clock. These spikes feed into a network of digital asynchronous processing elements or DAPES. By building a useful assemblage of DAPES, and connecting them together in the correct way, sophisticated signal processing can be accomplished within the focal plane. Autonomous self-resetting pixels (AsP) enable SPARR to generate electronic response with very small signals--as little as a single photon in the case of Geiger mode avalanche photodiodes to as few as several hundred photons for in-cmos photodetectors. These spiking pixels enable fast detector response, but do not draw as much continuous power as synchronous clocked designs. The spikes emitted by the pixels all have the same magnitude, the information from the scene is effectively encoded into the rate of spikes and the time at which the spike is emitted. The spiking pixels, having converted incident light into electronic spikes, supply the spikes to a network of digital asynchronous processors. These are small state machines which respond to the spikes arriving at their input ports by either remaining unchanged or updating their internal state and possibly emitting a spike on one or more output ports. We show a design that accomplishes the sophisticated signal processing of a Haar spatial wavelet transform with spatial-spectral whitening. We furthermore show how this design results in a data streams which support imaging and transient optical source detection. Two simulators support this analysis: SPICE and sparrow. The CMOS SPICE simulator Cadence provides accurate CMOs design with accounting for effects of circuit parasitics throughout layout, accurate timing, and accurate energy consumption estimates. To more rapidly assess larger networks with more pixels, sparrow is a custom discrete event simulator that supports the non-homogeneous Poisson processes that lie behind photoelectric interaction. Sparrow is a photon-exact simulator that nevertheless performs SPARR system simulator for large-scale systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mincey, John S.; Su, Eric C.; Silva-Martinez, Jose; Rodenbeck, Christopher T.
A configurable-bandwidth (BW) filter is presented in this paper for pulsed radar applications. To eliminate dispersion effects in the received waveform, a finite impulse response (FIR) topology is proposed, which has a measured standard deviation of an in-band group delay of 11 ns that is primarily dominated by the inherent, fully predictable delay introduced by the sample-and-hold. The filter operates at an IF of 20 MHz, and is tunable in BW from 1.5 to 15 MHz, which makes it optimal to be used with varying pulse widths in the radar. Employing a total of 128 taps, the FIR filter provides greater than 50-dB sharp attenuation in the stopband in order to minimize all out-of-band noise in the low signal-to-noise received radar signal. Fabricated in a 0.18-μm silicon on insulator CMOS process, the proposed filter consumes approximately 3.5 mW/tap with a 1.8-V supply. A 20-MHz two-tone measurement with 200-kHz tone separation shows IIP3 greater than 8.5 dBm.