Publications

Abstract not provided.

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor's scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Thus, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop's sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

Bulk 14-nm FinFET technology was irradiated in a heavy-ion environment (42-MeV Si ions) to study the possibility of displacement damage (DD) in scaled technology devices, resulting in drive current degradation with increased cumulative fluence. These devices were also exposed to an electron beam, proton beam, and cobalt-60 source (gamma radiation) to further elucidate the physics of the device response. Annealing measurements show minimal to no 'rebound' in the ON-state current back to its initial high value; however, the OFF-state current 'rebound' was significant for gamma radiation environments. Low-temperature experiments of the heavy-ion-irradiated devices reveal increased defect concentration as the result for mobility degradation with increased fluence. Furthermore, the subthreshold slope (SS) temperature dependence uncovers a possible mechanism of increased defect bulk traps contributing to tunneling at low temperatures. Simulation work in Silvaco technology computer-aided design (TCAD) suggests that the increased OFF-state current is a total ionizing dose (TID) effect due to oxide traps in the shallow trench isolation (STI). The significant SS elongation and ON-state current degradation could only be produced when bulk traps in the channel were added. Heavy-ion irradiation on bulk 14-nm FinFETs was found to be a combination of TID and DD effects.

Total ionizing dose response of 14-nm bulk-Si FinFETs has been studied with a specially designed test chip. The radiation testing shows evidence of interface trap build-up on 14-nm Bulk FinFET technologies. These defects created in the isolation layer give rise to a new radiation-induced leakage path which might lead to a reliability issue in CMOS technologies at or below the 14-nm node. TCAD simulations are performed and an analytical model for TID-induced leakage current is presented to support analysis of the identified TID mechanism. TCAD simulation and analytical model results are consistent with the experimental data.

Abstract not provided.