Publications

Abstract not provided.

Abstract not provided.

Abstract not provided.

Visible light laser voltage probing (LVP) for improved backside optical spatial resolution is demonstrated on ultra-thinned samples. A prototype system for data acquisition, a method to produce ultra-thinned SOI samples, and LVP signal, imaging, and waveform acquisition are described on early and advanced SOI technology nodes. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

We report Pauli blockade in a multielectron silicon metal–oxide–semiconductor double quantum dot with an integrated charge sensor. The current is rectified up to a blockade energy of 0.18 ± 0.03 meV. The blockade energy is analogous to singlet–triplet splitting in a two electron double quantum dot. Built-in imbalances of tunnel rates in the MOS DQD obfuscate some edges of the bias triangles. A method to extract the bias triangles is described, and a numeric rate-equation simulation is used to understand the effect of tunneling imbalances and finite temperature on charge stability (honeycomb) diagram, in particular the identification of missing and shifting edges. A bound on relaxation time of the triplet-like state is also obtained from this measurement.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Techniques for removing the back substrate of SOI devices are described for both packaged devices and devices at the die level. The use of these techniques for microbeam, heavy-ion, and laser testing are illustrated. © 2012 IEEE.

Resonant subwavelength gratings have been designed and fabricated as wavelength-specific reflectors for application as a rotary position encoder utilizing ebeam based photolithography. The first grating design used a two-dimensional layout to provide polarization insensitivity with separate layers for the grating and waveguide. The resulting devices had excellent pattern fidelity and the resonance peaks and widths closely matched the expected results. Unfortunately, the gratings were particularly angle sensitive and etch depth errors led to shifts in the center wavelength of the resonances. A second design iteration resulted in a double grating period to reduce the angle sensitivity as well as different materials and geometry; the grating and waveguide being the same layer. The inclusion of etch stop layers provided more accurate etch depths; however, the tolerance to changes in the grating duty cycle was much tighter. Results from these devices show the effects of small errors in the pattern fidelity. The fabrication process flows for both iterations of devices will be reviewed as well as the performance of the fabricated devices. A discussion of the relative merits of the various design choices provides insight into the importance of fabrication considerations during the design stage. © 2012 SPIE.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

Abstract not provided.

We fabricated a split-gate defined point contact in a double gate enhancement mode Si-MOS device, and implanted Sb donor atoms using a self-aligned process. E-beam lithography in combination with a timed implant gives us excellent control over the placement of dopant atoms, and acts as a stepping stone to focused ion beam implantation of single donors. Our approach allows us considerable latitude in experimental design in-situ. We have identified two resonance conditions in the point contact conductance as a function of split gate voltage. Using tunneling spectroscopy, we probed their electronic structure as a function of temperature and magnetic field. We also determine the capacitive coupling between the resonant feature and several gates. Comparison between experimental values and extensive quasi-classical simulations constrain the location and energy of the resonant level. We discuss our results and how they may apply to resonant tunneling through a single donor.

Abstract not provided.

Abstract not provided.

The amounts of charge collection by single-photon absorption to that by two-photon absorption laser testing techniques have been directly compared using specially made SOI diodes. Details of this comparison are discussed.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Using a two-step method of plasma and wet chemical etching, we demonstrate smooth, vertical facets for use in Al{sub x} Ga{sub 1-x} N-based deep-ultraviolet laser-diode heterostructures where x = 0 to 0.5. Optimization of plasma-etching conditions included increasing both temperature and radiofrequency (RF) power to achieve a facet angle of 5 deg from vertical. Subsequent etching in AZ400K developer was investigated to reduce the facet surface roughness and improve facet verticality. The resulting combined processes produced improved facet sidewalls with an average angle of 0.7 deg from vertical and less than 2-nm root-mean-square (RMS) roughness, yielding an estimated reflectivity greater than 95% of that of a perfectly smooth and vertical facet.

There is significant interest in forming quantum bits (qubits) out of single electron devices for quantum information processing (QIP). Information can be encoded using properties like charge or spin. Spin is appealing because it is less strongly coupled to the solid-state environment so it is believed that the quantum state can better be preserved over longer times (i.e., that is longer decoherence times may be achieved). Long spin decoherence times would allow more complex qubit operations to be completed with higher accuracy. Recently spin qubits were demonstrated by several groups using electrostatically gated modulation doped GaAs double quantum dots (DQD) [1], which represented a significant breakthrough in the solid-state field. Although no Si spin qubit has been demonstrated to date, work on Si and SiGe based spin qubits is motivated by the observation that spin decoherence times can be significantly longer than in GaAs. Spin decoherence times in GaAs are in part limited by the random spectral diffusion of the non-zero nuclear spins of the Ga and As that couple to the electron spin through the hyperfine interaction. This effect can be greatly suppressed by using a semiconductor matrix with a near zero nuclear spin background. Near zero nuclear spin backgrounds can be engineered using Si by growing {sup 28}Si enriched epitaxy. In this talk, we will present fabrication details and electrical transport results of an accumulation mode double top gated Si metal insulator semiconductor (MIS) nanostructure, Fig 1 (a) & (b). We will describe how this single electron device structure represent a path towards forming a Si based spin qubit similar in design as that demonstrated in GaAs. Potential advantages of this novel qubit structure relative to previous approaches include the combination of: no doping (i.e., not modulation doped); variable two-dimensional electron gas (2DEG) density; CMOS compatible processes; and relatively small vertical length scales to achieve smaller dots. A primary concern in this structure is defects at the insulator-silicon interface. The Sandia National Laboratories 0.35 {micro}m fab line was used for critical processing steps including formation of the gate oxide to examine the utility of a standard CMOS quality oxide silicon interface for the purpose of fabricating Si qubits. Large area metal oxide silicon (MOS) structures showed a peak mobility of 15,000 cm{sup 2}/V-s at electron densities of {approx}1 x 10{sup 12} cm{sup -2} for an oxide thickness of 10 nm. Defect density measured using standard C-V techniques was found to be greater with decreasing oxide thickness suggesting a device design trade-off between oxide thickness and quantum dot size. The quantum dot structure is completed using electron beam lithography and poly-silicon etch to form the depletion gates, Fig 1 (a). The accumulation gate is added by introducing a second insulating Al{sub 2}O{sub 3} layer, deposited by atomic layer deposition, followed by an Al top gate deposition, Fig. 1 (b). Initial single electron transistor devices using SiO{sub 2} show significant disorder in structures with relatively large critical dimensions of the order of 200-300 nm, Fig 2. This is not uncommon for large silicon structures and has been cited in the literature [2]. Although smaller structures will likely minimize the effect of disorder and well controlled small Si SETs have been demonstrated [3], the design constraints presented by disorder combined with long term concerns about effects of defects on spin decoherence time (e.g., paramagnetic centers) motivates pursuit of a 2nd generation structure that uses a compound semiconductor approach, an epitaxial SiGe barrier as shown in Fig. 2 (c). SiGe may be used as an electron barrier when combined with tensilely strained Si. The introduction of strained-Si into the double top gated device structure, however, represents additional fabrication challenges. Thermal budget is potentially constrained due to concerns related to strain relaxation. Fabrication details related to the introduction of strained silicon on insulator and SiGe barrier formation into the Sandia National Laboratories 0.35 {micro}m fab line will also be presented.

Abstract not provided.

Abstract not provided.

Abstract not provided.

We describe the development of a novel silicon quantum bit (qubit) device architecture that involves using materials that are compatible with a Sandia National Laboratories (SNL) 0.35 mum complementary metal oxide semiconductor (CMOS) process intended to operate at 100 mK. We describe how the qubit structure can be integrated with CMOS electronics, which is believed to have advantages for critical functions like fast single electron electrometry for readout compared to current approaches using radio frequency techniques. Critical materials properties are reviewed and preliminary characterization of the SNL CMOS devices at 4.2 K is presented.

Abstract not provided.

Abstract not provided.

Abstract not provided.