SPACEWIRE IN THE JOINT ARCHITECTURE STANDARD
Abstract not provided.
Publications
JAS interconnect requirement analysis and background
Abstract not provided.
Implementing CCSDS in the Joint Architecture Standard (JAS)
Abstract not provided.
Dynamic partial reconfiguration of softcore processors on the Virtex 5
Abstract not provided.
Flexible Space Computing Architectures and the Role of FPGAs
Abstract not provided.
Sandia-Xilinx Virtex FPGA SEU Experiment on the International Space Station
Abstract not provided.
JAS Overview
Abstract not provided.
Sandia-Xilinx Virtex FPGA SEU Experiment on the International Space Station
Abstract not provided.
Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array
Abstract not provided.
Sandia-Xilinx Virtex FPGA SEU Experiment on the International Space Station
Abstract not provided.
Virtex-5 softcore processing daughtercard
Abstract not provided.
Bitstream compression through frame removal and partial reconfiguration
FPL 09: 19th International Conference on Field Programmable Logic and Applications
As FPGA logic density continues to increase, new techniques are needed to store initial configuration data efficiently, maintain usability, and minimize cost. In this paper, a novel compression technique is presented for Xilinx Virtex partially reconfigurable FPGAs. This technique relies on constrained hardware design and layout combined with a few simple compression techniques. This technique uses partial recon-figuration to separate a hardware design into two separate regions: a static and partial region. A bitstream containing only the static region is then compressed by removing empty frames. This bitstream will be stored in non-volatile memory and used for initialization. The remaining logic is configured through partial reconfiguration over a communication network. By applying this technique, a high level of compression was achieved (almost 90% for the V4 LX25). This compression technique requires no extra decompression circuitry and compression levels improve as device size increases. ©2009 IEEE.
Partial Reconfiguration via Configuration Scrubbing
Abstract not provided.
A study of node-based architectures for satellite systems
Abstract not provided.
Single Event Upset Xilinx-Sandia Experiment (SEUXSE) and Sandia Passive ISS Research Experiment (SPIRE)
Abstract not provided.
A Study of Node Based Architectures for Satellite Systems
Abstract not provided.
Network topology analysis
Emerging high-bandwidth, low-latency network technology has made network-based architectures both feasible and potentially desirable for use in satellite payload architectures. The selection of network topology is a critical component when developing these multi-node or multi-point architectures. This study examines network topologies and their effect on overall network performance. Numerous topologies were reviewed against a number of performance, reliability, and cost metrics. This document identifies a handful of good network topologies for satellite applications and the metrics used to justify them as such. Since often multiple topologies will meet the requirements of the satellite payload architecture under development, the choice of network topology is not easy, and in the end the choice of topology is influenced by both the design characteristics and requirements of the overall system and the experience of the developer.
17 Results