This manual describes the installation and use of the Xyce™ XDM Netlist Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice, HSPICE, and Spectre netlists into Xyce™ netlists.
This manual describes the use of the Xyce™ Parallel Electronic Simulator. Xyce™ has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: (1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. (2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. (3) Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only). (4) Object-oriented code design and implementation using modern coding practices. Xyce™ is a parallel code in the most general sense of the phrase—a message passing parallel implementation—which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel eficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce™ Parallel Electronic Simulator, and is a companion document to the Xyce™ Users' Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce™. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce™ Users' Guide.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: (1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. (2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. (3) Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only). (4) Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide.
This manual describes the installation and use of the Xyce™ XDM Netlist Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice, HSPICE, and Spectre netlists into Xyce™ netlists.
Abstract not provided.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: • Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. • A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. • Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). • Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide.
This manual describes the installation and use of the Xyce™ XDM Netlist Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice, HSPICE, and Spectre netlists into Xyce™ netlists.
Abstract not provided.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers; A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models; Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only); Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase—a message passing parallel implementation—which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This manual describes the installation and use of the Xyce™ XDM Netlist Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice, HSPICE, and Spectre netlists into Xyce™ netlists.
This manual describes the installation and use of the XyceTM XDM Net list Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice and HSPICE netlists into XyceTM netlists.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: 1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. 2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. 3) Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only). 4) Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase a message passing parallel implementation which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
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This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been de- signed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel com- puting platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase -- a message passing parallel implementation -- which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide [1] . The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce . This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide [1] . Copyright c 2002 National Technology & Engineering Solutions of Sandia, LLC (NTESS). Acknowledgements We would like to acknowledge all the code and test suite developers who have contributed to the Xyce project over the years: Alan Lundin, Arlon Waters, Ashley Meek, Bart van Bloemen Waanders, Brad Bond, Brian Fett, Christina Warrender, David Baur, David Day, David Shirley, Deborah Fixel, Derek Barnes, Eric Rankin, Erik Zeek, Gary Hennigan, Herman "Buddy" Watts, Jim Emery, Keith Santarelli, Laura Boucheron, Lawrence Musson, Mary Meinelt, Mingyu "Genie" Hsieh, Nicholas Johnson, Philip Campbell, Rebecca Arnold, Regina Schells, Richard Drake, Robert Hoekstra, Roger Pawlowski, Russell Hooper, Samuel Browne, Scott Hutchinson, Smitha Sam, Steven Verzi, Tamara Kolda, Timur Takhtaganov, and Todd Coffey. Also, thanks to Hue Lai for the original typesetting of this document in L A T E X. Trademarks Xyce Electronic Simulator TM and Xyce TM are trademarks of National Technology & Engineering Solutions of Sandia, LLC (NTESS). All other trademarks are property of their respective owners. Contact Information Outside Sandia World Wide Web http://xyce.sandia.gov Email xyce@sandia.gov Inside Sandia World Wide Web http://xyce.sandia.gov Email xyce-sandia@sandia.gov Bug Reports http://joseki-vm.sandia.gov/bugzilla http://morannon.sandia.gov/bugzilla
Abstract not provided.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce . This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been de- signed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel com- puting platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase$-$ a message passing parallel implementation $-$ which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide [1] . The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce . This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide [1] . The information herein is subject to change without notice. Copyright c 2002-2017 Sandia Corporation. All rights reserved. Trademarks Xyce TM Electronic Simulator and Xyce TM are trademarks of Sandia Corporation. Orcad, Orcad Capture, PSpice and Probe are registered trademarks of Cadence Design Systems, Inc. Microsoft, Windows and Windows 7 are registered trademarks of Microsoft Corporation. Medici, DaVinci and Taurus are registered trademarks of Synopsys Corporation. Amtec and TecPlot are trademarks of Amtec Engineering, Inc. All other trademarks are property of their respective owners. Contacts World Wide Web http://xyce.sandia.gov https://info.sandia.gov/xyce (Sandia only) Email xyce@sandia.gov (outside Sandia) xyce-sandia@sandia.gov (Sandia only) Bug Reports (Sandia only) http://joseki-vm.sandia.gov/bugzilla http://morannon.sandia.gov/bugzilla
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel com- puting platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase -- a message passing parallel implementation -- which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. The information herein is subject to change without notice. Copyright c 2002-2017 Sandia Corporation. All rights reserved. Trademarks Xyce TM Electronic Simulator and Xyce TM are trademarks of Sandia Corporation. Orcad, Orcad Capture, PSpice and Probe are registered trademarks of Cadence Design Systems, Inc. Microsoft, Windows and Windows 7 are registered trademarks of Microsoft Corporation. Medici, DaVinci and Taurus are registered trademarks of Synopsys Corporation. Amtec and TecPlot are trademarks of Amtec Engineering, Inc. All other trademarks are property of their respective owners. Contacts World Wide Web http://xyce.sandia.gov https://info.sandia.gov/xyce (Sandia only) Email xyce@sandia.gov (outside Sandia) xyce-sandia@sandia.gov (Sandia only) Bug Reports (Sandia only) http://joseki-vm.sandia.gov/bugzilla http://morannon.sandia.gov/bugzilla
Abstract not provided.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide [1] . The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce . This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide [1] . The information herein is subject to change without notice. Copyright c 2002-2016 Sandia Corporation. All rights reserved. Acknowledgements The BSIM Group at the University of California, Berkeley developed the BSIM3, BSIM4, BSIM6, BSIM-CMG and BSIM-SOI models. The BSIM3 is Copyright c 1999, Regents of the University of California. The BSIM4 is Copyright c 2006, Regents of the University of California. The BSIM6 is Copyright c 2015, Regents of the University of California. The BSIM-CMG is Copyright c 2012 and 2016, Regents of the University of California. The BSIM-SOI is Copyright c 1990, Regents of the University of California. All rights reserved. The Mextram model has been developed by NXP Semiconductors until 2007, Delft University of Technology from 2007 to 2014, and Auburn University since April 2015. Copyrights c of Mextram are with Delft University of Technology, NXP Semiconductors and Auburn University. The MIT VS Model Research Group developed the MIT Virtual Source (MVS) model. Copyright c 2013 Massachusetts Institute of Technology (MIT). The EKV3 MOSFET model was developed by the EKV Team of the Electronics Laboratory-TUC of the Technical University of Crete. Trademarks Xyce TM Electronic Simulator and Xyce TM are trademarks of Sandia Corporation. Orcad, Orcad Capture, PSpice and Probe are registered trademarks of Cadence Design Systems, Inc. Microsoft, Windows and Windows 7 are registered trademarks of Microsoft Corporation. Medici, DaVinci and Taurus are registered trademarks of Synopsys Corporation. Amtec and TecPlot are trademarks of Amtec Engineering, Inc. All other trademarks are property of their respective owners. Contacts World Wide Web http://xyce.sandia.gov https://info.sandia.gov/xyce (Sandia only) Email xyce@sandia.gov (outside Sandia) xyce-sandia@sandia.gov (Sandia only) Bug Reports (Sandia only) http://joseki-vm.sandia.gov/bugzilla http://morannon.sandia.gov/bugzilla
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been de- signed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel com- puting platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase -- a message passing parallel implementation -- which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. The information herein is subject to change without notice. Copyright c 2002-2016 Sandia Corporation. All rights reserved. Acknowledgements The BSIM Group at the University of California, Berkeley developed the BSIM3, BSIM4, BSIM6, BSIM-CMG and BSIM-SOI models. The BSIM3 is Copyright c 1999, Regents of the University of California. The BSIM4 is Copyright c 2006, Regents of the University of California. The BSIM6 is Copyright c 2015, Regents of the University of California. The BSIM-CMG is Copyright c 2012 and 2016, Regents of the University of California. The BSIM-SOI is Copyright c 1990, Regents of the University of California. All rights reserved. The Mextram model has been developed by NXP Semiconductors until 2007, Delft University of Technology from 2007 to 2014, and Auburn University since April 2015. Copyrights c of Mextram are with Delft University of Technology, NXP Semiconductors and Auburn University. The MIT VS Model Research Group developed the MIT Virtual Source (MVS) model. Copyright c 2013 Massachusetts Institute of Technology (MIT). The EKV3 MOSFET model was developed by the EKV Team of the Electronics Laboratory-TUC of the Technical University of Crete. Trademarks Xyce TM Electronic Simulator and Xyce TM are trademarks of Sandia Corporation. Orcad, Orcad Capture, PSpice and Probe are registered trademarks of Cadence Design Systems, Inc. Microsoft, Windows and Windows 7 are registered trademarks of Microsoft Corporation. Medici, DaVinci and Taurus are registered trademarks of Synopsys Corporation. Amtec and TecPlot are trademarks of Amtec Engineering, Inc. All other trademarks are property of their respective owners. Contacts World Wide Web http://xyce.sandia.gov https://info.sandia.gov/xyce (Sandia only) Email xyce@sandia.gov (outside Sandia) xyce-sandia@sandia.gov (Sandia only) Bug Reports (Sandia only) http://joseki-vm.sandia.gov/bugzilla http://morannon.sandia.gov/bugzilla
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase -- a message passing parallel implementation -- which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. The information herein is subject to change without notice. Copyright © 2002-2016 Sandia Corporation. All rights reserved.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users’ Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users’ Guide. The information herein is subject to change without notice. Copyright © 2002-2016 Sandia Corporation. All rights reserved.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been de- signed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel com- puting platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase -- a message passing parallel implementation -- which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. Trademarks The information herein is subject to change without notice. Copyright c 2002-2015 Sandia Corporation. All rights reserved. Xyce TM Electronic Simulator and Xyce TM are trademarks of Sandia Corporation. Portions of the Xyce TM code are: Copyright c 2002, The Regents of the University of California. Produced at the Lawrence Livermore National Laboratory. Written by Alan Hindmarsh, Allan Taylor, Radu Serban. UCRL-CODE-2002-59 All rights reserved. Orcad, Orcad Capture, PSpice and Probe are registered trademarks of Cadence Design Systems, Inc. Microsoft, Windows and Windows 7 are registered trademarks of Microsoft Corporation. Medici, DaVinci and Taurus are registered trademarks of Synopsys Corporation. Amtec and TecPlot are trademarks of Amtec Engineering, Inc. Xyce 's expression library is based on that inside Spice 3F5 developed by the EECS Department at the University of California. The EKV3 MOSFET model was developed by the EKV Team of the Electronics Laboratory-TUC of the Technical University of Crete. All other trademarks are property of their respective owners. Contacts Bug Reports (Sandia only) http://joseki.sandia.gov/bugzilla http://charleston.sandia.gov/bugzilla World Wide Web http://xyce.sandia.gov http://charleston.sandia.gov/xyce (Sandia only) Email xyce@sandia.gov (outside Sandia) xyce-sandia@sandia.gov (Sandia only)
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide [1] . The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce . This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide [1] . Trademarks The information herein is subject to change without notice. Copyright c 2002-2015 Sandia Corporation. All rights reserved. Xyce TM Electronic Simulator and Xyce TM are trademarks of Sandia Corporation. Portions of the Xyce TM code are: Copyright c 2002, The Regents of the University of California. Produced at the Lawrence Livermore National Laboratory. Written by Alan Hindmarsh, Allan Taylor, Radu Serban. UCRL-CODE-2002-59 All rights reserved. Orcad, Orcad Capture, PSpice and Probe are registered trademarks of Cadence Design Systems, Inc. Microsoft, Windows and Windows 7 are registered trademarks of Microsoft Corporation. Medici, DaVinci and Taurus are registered trademarks of Synopsys Corporation. Amtec and TecPlot are trademarks of Amtec Engineering, Inc. Xyce 's expression library is based on that inside Spice 3F5 developed by the EECS Department at the University of California. The EKV3 MOSFET model was developed by the EKV Team of the Electronics Laboratory-TUC of the Technical University of Crete. All other trademarks are property of their respective owners. Contacts Bug Reports (Sandia only) http://joseki.sandia.gov/bugzilla http://charleston.sandia.gov/bugzilla World Wide Web http://xyce.sandia.gov http://charleston.sandia.gov/xyce (Sandia only) Email xyce@sandia.gov (outside Sandia) xyce-sandia@sandia.gov (Sandia only)
We present results from laser annealing experiments in Si using a passively Q-switched Nd:YAG microlaser. Exposure with laser at fluence values above the damage threshold of commercially available photodiodes results in electrical damage (as measured by an increase in photodiode dark current). We show that increasing the laser fluence to values in excess of the damage threshold can result in annealing of a damage site and a reduction in detector dark current by as much as 100x in some cases. A still further increase in fluence results in irreparable damage. Thus we demonstrate the presence of a laser annealing window over which performance of damaged detectors can be at least partially reconstituted. Moreover dark current reduction is observed over the entire operating range of the diode indicating that device performance has been improved for all values of reverse bias voltage. Additionally, we will present results of laser annealing in Si waveguides. By exposing a small (<10 um) length of a Si waveguide to an annealing laser pulse, the longitudinal phase of light acquired in propagating through the waveguide can be modified with high precision, <15 milliradian per laser pulse. Phase tuning by 180 degrees is exhibited with multiple exposures to one arm of a Mach-Zehnder interferometer at fluence values below the morphological damage threshold of an etched Si waveguide. No reduction in optical transmission at 1550 nm was found after 220 annealing laser shots. Modeling results for laser annealing in Si are also presented.
Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics
Demand for integration of near infrared optoelectronic functionality with silicon complementary metal oxide semiconductor (CMOS) technology has for many years motivated the investigation of low temperature germanium on silicon deposition processes. This work describes the development of a high density plasma chemical vapor deposition process that uses a low temperature (<460 °C) in situ germane/argon plasma surface preparation step for epitaxial growth of germanium on silicon. It is shown that the germane/argon plasma treatment sufficiently removes SiOx and carbon at the surface to enable germanium epitaxy. The use of this surface preparation step demonstrates an alternative way to produce germanium epitaxy at reduced temperatures, a key enabler for increased flexibility of integration with CMOS back-end-of-line fabrication.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been de- signed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel com- puting platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase -- a message passing parallel implementation -- which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. Trademarks The information herein is subject to change without notice. Copyright c 2002-2014 Sandia Corporation. All rights reserved. Xyce TM Electronic Simulator and Xyce TM are trademarks of Sandia Corporation. Portions of the Xyce TM code are: Copyright c 2002, The Regents of the University of California. Produced at the Lawrence Livermore National Laboratory. Written by Alan Hindmarsh, Allan Taylor, Radu Serban. UCRL-CODE-2002-59 All rights reserved. Orcad, Orcad Capture, PSpice and Probe are registered trademarks of Cadence Design Systems, Inc. Microsoft, Windows and Windows 7 are registered trademarks of Microsoft Corporation. Medici, DaVinci and Taurus are registered trademarks of Synopsys Corporation. Amtec and TecPlot are trademarks of Amtec Engineering, Inc. Xyce 's expression library is based on that inside Spice 3F5 developed by the EECS Department at the University of California. The EKV3 MOSFET model was developed by the EKV Team of the Electronics Laboratory-TUC of the Technical University of Crete. All other trademarks are property of their respective owners. Contacts Bug Reports (Sandia only) http://joseki.sandia.gov/bugzilla http://charleston.sandia.gov/bugzilla World Wide Web http://xyce.sandia.gov http://charleston.sandia.gov/xyce (Sandia only) Email xyce@sandia.gov (outside Sandia) xyce-sandia@sandia.gov (Sandia only)
The highlights of the Xyce 6.1 release are documented.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas; Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers; A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models; Device models that are specifically tailored to meet Sandia's needs, including some radiationaware devices (for Sandia users only); and Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase-a message passing parallel implementation-which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users<U+2019> Guide [1] . The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users<U+2019> Guide [1] .
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This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users
Proceedings of SPIE - The International Society for Optical Engineering
We present results from laser annealing experiments in Si using a passively Q-switched Nd:YAG microlaser. Exposure with laser at fluence values above the damage threshold of commercially available photodiodes results in electrical damage (as measured by an increase in photodiode dark current). We show that increasing the laser fluence to values in excess of the damage threshold can result in annealing of a damage site and a reduction in detector dark current by as much as 100x in some cases. A still further increase in fluence results in irreparable damage. Thus we demonstrate the presence of a laser annealing window over which performance of damaged detectors can be at least partially reconstituted. Moreover dark current reduction is observed over the entire operating range of the diode indicating that device performance has been improved for all values of reverse bias voltage. Additionally, we will present results of laser annealing in Si waveguides. By exposing a small (<10 um) length of a Si waveguide to an annealing laser pulse, the longitudinal phase of light acquired in propagating through the waveguide can be modified with high precision, <15 milliradian per laser pulse. Phase tuning by 180 degrees is exhibited with multiple exposures to one arm of a Mach-Zehnder interferometer at fluence values below the morphological damage threshold of an etched Si waveguide. No reduction in optical transmission at 1550 nm was found after 220 annealing laser shots. © 2014 SPIE.
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The highlights of the Xyce 6.0.1 release are documented.
While Xyce uses the Autoconf and Automake system to configure builds, it is often necessary to perform more than the customary %E2%80%9C./configure%E2%80%9D builds many open source users have come to expect. This document describes the steps needed to get Xyce built on a number of common platforms.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users
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Photocurrent generated by ionizing radiation represents a threat to microelectronics in radiation environments. Circuit simulation tools such as SPICE [1] can be used to analyze these threats, and typically rely on compact models for individual electrical components such as transistors and diodes. Compact models consist of a handful of differential and/or algebraic equations, and are derived by making simplifying assumptions to any of the many semiconductor transport equations. Historically, many photocurrent compact models have suffered from accuracy issues due to the use of qualitative approximation, rather than mathematically correct solutions to the ambipolar diffusion equation. A practical consequence of this inaccuracy is that a given model calibration is trustworthy over only a narrow range of operating conditions. This report describes work to produce improved compact models for photocurrent. Specifically, an analytic model is developed for epitaxial diode structures that have a highly doped subcollector. The analytic model is compared with both numerical TCAD calculations, as well as the compact model described in reference [2]. The new analytic model compares well against TCAD over a wide range of operating conditions, and is shown to be superior to the compact model from reference [2].
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Proceedings of SPIE - The International Society for Optical Engineering
We have developed a system to measure the directional thermal emission from a surface, and in turn, calculate its emissivity. This approach avoids inaccuracies sometimes encountered with the traditional method for calculating emissivity, which relies upon subtracting the measured total reflectivity and total transmissivity from unity. Typical total reflectivity measurements suffer from an inability to detect backscattered light, and may not be accurate for high angles of incidence. Our design allows us to vary the measurement angle (θ) from near-normal to ∼80°, and can accommodate samples as small as 7 mm on a side by controlling the sample interrogation area. The sample mount is open-backed to eliminate shine-through, can be heated up to 200°C, and is kept under vacuum to avoid oxidizing the sample. A cold shield reduces the background noise and stray signals reflected off the sample. We describe the strengths, weaknesses, trade-offs, and limitations of our system design, data analysis methods, the measurement process, and present the results of our validation of this Variable-Angle Directional Emissometer.
Photonics and Nanostructures - Fundamentals and Applications
An accurate methodology is presented to measure photonic crystal emissivity using a direct method. This method addresses the issue of how to separate the emissions from the photonic crystal and the substrate. The method requires measuring two quantities: the total emissivity of the photonic crystal-substrate system, and the emissivity of the substrate alone. Our measurements have an uncertainty of 4% and represent the most accurate measure of a photonic crystal's emissivity. The measured results are compared to, and agree very well with, the independent emitter model. © 2007 Elsevier B.V. All rights reserved.
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Proceedings of SPIE - The International Society for Optical Engineering
The LIGA microfabrication technique offers a unique method for fabricating 3-dimensional photonic lattices based on the Iowa State "logpile" structure. These structures represent the [111] orientation of the [100] logpile structures previously demonstrated by Sandia National Laboratories, The novelty to this approach is the single step process that does not require any alignment. The mask and substrate are fixed to one another and exposed twice from different angles using a synchrotron light source. The first exposure patterns the resist at an angle of 45 degrees normal to the substrate with a rotation of 8 degrees. The second exposure requires a 180 degree rotation about the normal of the mask and substrate. The resulting pattern is a vertically oriented logpile pattern that is rotated slightly off axis. The exposed PMMA is developed in a single step to produce an inverse lattice structure. This mold is filled with electroplated gold and stripped away to create a usable gold photonic crystal. Tilted logpiles demonstrate band characteristics very similar to those observed from [100] logpiles. Reflectivity tests show a band edge around 5 μm and compare well with numerical simulations.
The silicon microelectronics industry is the technological driver of modern society. The whole industry is built upon one major invention--the solid-state transistor. It has become clear that the conventional transistor technology is approaching its limitations. Recent years have seen the advent of magnetoelectronics and spintronics with combined magnetism and solid state electronics via spin-dependent transport process. In these novel devices, both charge and spin degree freedoms can be manipulated by external means. This leads to novel electronic functionalities that will greatly enhance the speed of information processing and memory storage density. The challenge lying ahead is to understand the new device physics, and control magnetic phenomena at nanometer length scales and in reduced dimensions. To meet this goal, we proposed the silicon nanocrystal system, because: (1) It is compatible with existing silicon fabrication technologies; (2) It has shown strong quantum confinement effects, which can modify the electric and optical properties through directly modifying the band structure; and (3) the spin-orbital coupling in silicon is very small, and for isotopic pure {sup 28}Si, the nuclear spin is zero. These will help to reduce the spin-decoherence channels. In the past fiscal year, we have studied the growth mechanism of silicon-nanocrystals embedded in silicon dioxide, their photoluminescence properties, and the Si-nanocrystal's magnetic properties in the presence of Mn-ion doping. Our results may demonstrate the first evidence of possible ferromagnetic orders in Mn-ion implanted silicon nanocrystals, which can lead to ultra-fast information process and ultra-dense magnetic memory applications.
The potential for electrochromic (EC) materials to be incorporated into a Fabry-Perot (FP) filter to allow modest amounts of tuning was evaluated by both experimental methods and modeling. A combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), and electrochemical methods was used to produce an ECFP film stack consisting of an EC WO{sub 3}/Ta{sub 2}O{sub 5}/NiO{sub x}H{sub y} film stack (with indium-tin-oxide electrodes) sandwiched between two Si{sub 3}N{sub 4}/SiO{sub 2} dielectric reflector stacks. A process to produce a NiO{sub x}H{sub y} charge storage layer that freed the EC stack from dependence on atmospheric humidity and allowed construction of this complex EC-FP stack was developed. The refractive index (n) and extinction coefficient (k) for each layer in the EC-FP film stack was measured between 300 and 1700 nm. A prototype EC-FP filter was produced that had a transmission at 500 nm of 36%, and a FWHM of 10 nm. A general modeling approach that takes into account the desired pass band location, pass band width, required transmission and EC optical constants in order to estimate the maximum tuning from an EC-FP filter was developed. Modeling shows that minor thickness changes in the prototype stack developed in this project should yield a filter with a transmission at 600 nm of 33% and a FWHM of 9.6 nm, which could be tuned to 598 nm with a FWHM of 12.1 nm and a transmission of 16%. Additional modeling shows that if the EC WO{sub 3} absorption centers were optimized, then a shift from 600 nm to 598 nm could be made with a FWHM of 11.3 nm and a transmission of 20%. If (at 600 nm) the FWHM is decreased to 1 nm and transmission maintained at a reasonable level (e.g. 30%), only fractions of a nm of tuning would be possible with the film stack considered in this study. These tradeoffs may improve at other wavelengths or with EC materials different than those considered here. Finally, based on our limited investigation and material set, the severe absorption associated with the refractive index change suggests that incorporating EC materials into phase correcting spatial light modulators (SLMS) would allow for only negligible phase correction before transmission losses became too severe. However, we would like to emphasize that other EC materials may allow sufficient phase correction with limited absorption, which could make this approach attractive.
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Materials Research Society Symposium Proceedings
Demand for integration of optoelectronic functionality (e.g., optical interconnects) with silicon complementary metal oxide semiconductor (CMOS) technology has for many years motivated the investigation of low temperature (∼450°C) germanium deposition processes that may be integrated in to the back-end CMOS process flow. A common challenge to improving the germanium quality is the thermal budget of the in-situ bake, which is used to reduce defect forming oxygen and carbon surface residues [1, 2]. Typical cleaning temperatures to remove significant concentrations of oxygen and carbon have been reported to be approximately 750°C for thermal hydrogen bakes in standard chemical vapor deposition chambers [3]. Germanium device performance using lower peak in-situ cleans (i.e., ∼450°C) has been hampered by additional crystal defectivity, although epitaxy is possible with out complete removal of oxygen and carbon at lower temperatures [4]. Plasma enhanced chemical vapor deposition (PECVD) is used to reduce the processing temperature. Hydrogen plasma assisted in-situ surface preparation of epitaxy has been shown to reduce both carbon and oxygen concentrations and enable epitaxial growth at temperatures as low as ∼150°C [5,6]. The hydrogen is believed to help produce volatile Si-O and H2O species in the removal of oxygen, although typically this is not reported to occur rapidly enough to completely clear the surface of all oxygen until ∼550°C. In this paper, we describe the use of an in-situ argon/germane high density plasma to help initiate germanium epitaxy on silicon using a peak temperature of approximately 460°C, Germanium is believed to readily break Si-O bonds to form more volatile Ge-O [7-9], therefore, argon/germane plasmas offer the potential to reduce the necessary in-situ clean temperature while obtaining similar results as hydrogen in-situ cleans. To the authors knowledge this report is also the first demonstration of germanium epitaxy on silicon using this commercially available high density plasma chamber configuration instead of, for example, remote or electron cyclotron resonance configurations. © 2006 Materials Research Society.
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Electrochromic (EC) materials are used in 'smart' windows that can be darkened by applying a voltage across an EC stack on the window. The associated change in refractive index (n) in the EC materials might allow their use in tunable or temperature-insensitive Fabry-Perot filters and transmissive-spatial-light-modulators (SLMs). The authors are conducting a preliminary evaluation of these materials in many applications, including target-in-the-loop systems. Data on tungsten oxide, WO{sub 3}, the workhorse EC material, indicate that it's possible to achieve modest changes in n with only slight increases in absorption between the visible and {approx}10 {micro}m. This might enable construction of a tunable Fabry-Perot filter consisting of an active EC layer (e.g. WO{sub 3}) and a proton conductor (e.g.Ta{sub 2}O{sub 5}) sandwiched between two gold electrodes. A SLM might be produced by replacing the gold with a transparent conductor (e.g. ITO). This SLM would allow broad-band operation like a micromirror array. Since it's a transmission element, simple optical designs like those in liquid-crystal systems would be possible. Our team has fabricated EC stacks and characterized their switching speed and optical properties (n, k). We plan to study the interplay between process parameters, film properties, and performance characteristics associated with the FP-filter and then extend what we learn to SLMs. Our goals are to understand whether the changes in absorption associated with changes in n are acceptable, and whether it's possible to design an EC-stack that's fast enough to be interesting. We'll present our preliminary findings regarding the potential viability of EC materials for target-in-the-loop applications.