Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor $I$-$V$ characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e., positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. The suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III-V/Si heterogeneously integrated electronics.
Wafer-level step-stress experiments on high voltage Npn InGaP/GaAs HBTs are presented. A methodology utilizing brief, monotonically increasing stresses and periodic, interrupted parametric characterization is presented. The method and various examples of step-stressed HBTs illustrate the value of the technique for screening the reliability of HBT wafers. Degradation modes observed in these InGaP/GaAs HBTs closely correspond to a subset of those in other, longer types of reliability experiments and can be relevant in a reliability screen. A statistical sampling of HBT wafers reveals a consistently realized critical destructive limit over a very narrow power range, which indicates that thermal stress is the main cause of degradation. When stepped just shy of the destructive limit, electrical characteristics are capable of revealing gradual degradation. The end state of stressing typically involves shorting of both the base-emitter and base-collector junctions. Interrupted characterization revealed cases where baseemitter shorts preceded base-collector shorts and other cases where base-collector shorts occurred first. Examples of degradation include reductions in reverse breakdown voltage, increases in the offset voltage, and drops in current gain. These wafer-level stepstress techniques show promise for reducing the large time lag between wafer fabrication and useful reliability screening in HBTs.
Results of several experiments aimed at remedying photoresist adhesion failure during spray wet chemical etching of InGaP/GaAs NPN HBTs are reported. Several factors were identified that could influence adhesion and a Design of Experiment (DOE) approach was used to study the effects and interactions of selected factors. The most significant adhesion improvement identified is the incorporation of a native oxide etch immediately prior to the photoresist coat. In addition to improving adhesion, this pre-coat treatment also alters the wet etch profile of (100) GaAs so that the reaction limited etch is more isotropic compared to wafers without surface treatment; the profiles have a positive taper in both the [011] and [011] directions, but the taper angles are not identical. The altered profiles have allowed us to predictably yield fully probe-able HBTs with 5 x 5 {micro}m emitters using 5200 {angstrom} evaporated metal without planarization.
This paper describes the development and implementation of an integrated resistor process based on reactively sputtered tantalum nitride. Image reversal lithography was shown to be a superior method for liftoff patterning of these films. The results of a response surface DOE for the sputter deposition of the films are discussed. Several approaches to stabilization baking were examined and the advantages of the hot plate method are shown. In support of a new capability to produce special-purpose HBT-based Small-Scale Integrated Circuits (SSICs), we developed our existing TaN resistor process, designed for research prototyping, into one with greater maturity and robustness. Included in this work was the migration of our TaN deposition process from a research-oriented tool to a tool more suitable for production. Also included was implementation and optimization of a liftoff process for the sputtered TaN to avoid the complicating effects of subtractive etching over potentially sensitive surfaces. Finally, the method and conditions for stabilization baking of the resistors was experimentally determined to complete the full implementation of the resistor module. Much of the work to be described involves the migration between sputter deposition tools - from a Kurt J. Lesker CMS-18 to a Denton Discovery 550. Though they use nominally the same deposition technique (reactive sputtering of Ta with N{sup +} in a RF-excited Ar plasma), they differ substantially in their design and produce clearly different results in terms of resistivity, conformity of the film and the difference between as-deposited and stabilized films. We will describe the design of and results from the design of experiments (DOE)-based method of process optimization on the new tool and compare this to what had been used on the old tool.