SST/macro Manual
Abstract not provided.
Publications
An AMR Task Dependency Analysis and Communications Simulation Methodology
Abstract not provided.
A Synthetic Task Model for HPC-Grade Optical Network Performance Evaluation
Abstract not provided.
Presentation: Validating extreme-scale HPC simulation through Bayesian inference uncertainty quantification
Abstract not provided.
SST/macro: A coarse-grained simulation workflow
Abstract not provided.
The Role of Optical Links in HPC System Interconnects
Abstract not provided.
SST/macro primer
Abstract not provided.
Execution Models for Exascale- A Bottom-Up Approach -(EMBU)
Abstract not provided.
Tutorial on Modeling Exascale Applications with SST/macro and Eiger
Abstract not provided.
SST/macro: A Macroscale Event Simulator for Extreme-Scale Computing
Abstract not provided.
Validating the Simulation of Large-scale Parallel Applications Using Statistical Characteristics
Abstract not provided.
Probabilistic Schwarz Coupling for Fault-Tolerance and Scalability
Abstract not provided.
SST/macro: A Macroscale Event Simulator for Extreme-Scale Computing
Abstract not provided.
Automatic Extraction of Software Skeletons for Benchmarking Large-Scale Parallel Applications
Abstract not provided.
Using VTK to Represent HPC Simulations with SST/macro
Abstract not provided.
Validating extreme-scale HPC simulation through Bayesian inference uncertainty quantification
Abstract not provided.
Programming Scientific Applications Now for the Integration of Silicon Photonics
Abstract not provided.
The Role of Optical Links in HPC System Interconnects
Abstract not provided.
A Deep Dive Analysis of Hardware Design Trade-offs for Exascale Combustion Applications
Abstract not provided.
Decreasing network power with on-off links informed by scientific applications
Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013
As the tapering off of Moore's Law produces the need for more parallelism in high-performance applications, the parallel programming model becomes central to achieving and maintaining performance per watt on current and future computer architectures. In order for a programmer to exploit parallelism in a power-efficient way, a close interaction with an abstract machine model is necessary to remain cognizant of important power-performance tradeoffs. This work introduces Asynchronous Circuit Programming (ACP), a way of explicitly identifying application communication as circuits to allow the underlying hardware to better execute code, and for a programmer to pipeline the allocation of communication hardware resources with computation. We provide a case study in using a preliminary C++ implementation of ACP with multiple scientific applications that illustrates how hardware can make use of application knowledge, keeping up to 75% of links in a low-power state. © 2013 IEEE.
Multi-Layer Silicon Nanophotonic Network Chips for High-Performance Computing
Proposed for publication in Journal of Parallel and Distributed Computing.
Abstract not provided.
Eiger :
Abstract not provided.
Enabling Exascale Co-design with The Structural Simulation Toolkit
Abstract not provided.
SST/macro: A Macroscale Event Simulator for Exascale Co-&%23173-design
Abstract not provided.
Multi-Layer Silicon Nanophotonic Network Chips for High-Performance Computing
Abstract not provided.
SST: A Simulator for Exascale Co-design
Abstract not provided.
Evaluation Optimization and Application of Execution Models for Exascale Computing
Abstract not provided.
Coarse-Grain Simulation of Networks-on-Chip using SST/Macro
Abstract not provided.
28 Results