Publications

IEEE Transactions on Nuclear Science

Schwank, James R.; Shaneyfelt, Marty R.; Felix, James A.; Dodd, Paul E.; Baggio, J.; Ferlet-Cavrois, V.; Paillet, P.; Hash, Gerald L.; Flores, Richard S.; Massengill, L.W.; Blackmore, E.

The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80°C after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents. © 2006 IEEE.

IEEE Transactions on Nuclear Science

Schwank, James R.; Shaneyfelt, Marty R.; Baggio, J.; Dodd, Paul E.; Felix, James A.; Ferlet-Cavrois, V.; Paillet, P.; Lambert, D.; Sexton, Frederick W.; Hash, Gerald L.; Blackmore, E.

The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton energies and temperature. SRAMs from five different vendors were irradiated at proton energies from 20 to 500 MeV and at temperatures of 25° and 85°C. For the SRAMs and radiation conditions examined in this work, proton energy SEL thresholds varied from as low as 20 MeV to as high as 490 MeV. To gain insight into the observed effects, the heavy-ion SEL linear energy transfer (LET) thresholds of the SRAMs were measured and compared to high-energy transport calculations of proton interactions with different materials. For some SRAMs that showed proton-induced SEL, the heavy-ion SEL threshold LET was as high as 25 MeV-cm 2/mg. Proton interactions with Si cannot generate nuclear recoils with LETs this large. Our nuclear scattering calculations suggest that the nuclear recoils are generated by proton interactions with tungsten. Tungsten plugs are commonly used in most high-density ICs fabricated today, including SRAMs. These results demonstrate that for system applications where latchups cannot be tolerated, SEL hardness assurance testing should be performed at a proton energy at least as high as the highest proton energy present in the system environment. Moreover, the best procedure to ensure that ICs will be latchup free in proton environments may be to use a heavy-ion source with LETs ≥40 MeV-cm 2/mg. © 2005 IEEE.

Schwank, James R.; Shaneyfelt, Marty R.; Dodd, Paul E.; Felix, James A.; Hash, Gerald L.

Abstract not provided.

IEEE Transactions on Nuclear Science

Shaneyfelt, Marty R.; Tangyunyong, Paiboon T.; Hill, Thomas A.; Soden, Jerry M.; Flores, Richard S.; Schwank, James R.; Dodd, Paul E.; Hash, Gerald L.

Eliminating radiation-induced parasitic leakage paths in integrated circuits (ICs) is key to improving their total dose hardness. Semiconductor manufacturers can use a combination of design and/or process techniques to eliminate known radiation-induced parasitic leakage paths. However, unknown or critical radiation-induced parasitic leakage may still exist on fully processed ICs and it is extremely difficult (if not impossible) to identify these leakage paths based on radiation induced parametric degradation. We show that light emission microscopy can be used to identify the location of radiation-induced parasitic leakage paths in ICs. This is illustrated by using light emission microscopy to find radiation-induced parasitic leakage paths in partially-depleted silicon on insulator static random-access memories (SRAMs). Once leakage paths were identified, modifications were made to the SRAM design to improve the total dose radiation hardness of the SRAMs. Light emission microscopy should prove to be an important tool for the development of future radiation hardened technologies and devices.

Dodd, Paul E.; Shaneyfelt, Marty R.; Schwank, James R.; Hash, Gerald L.

Abstract not provided.

IEEE Transactions on Nuclear Science

Dodd, Paul E.; Shaneyfelt, Marty R.; Walsh, David S.; Schwank, James R.; Hash, Gerald L.; Jones, Rhonda L.; Draper, Bruce L.; Winokur, Peter S.

The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

IEEE Transactions on Nuclear Science

Shaneyfelt, Marty R.; Schwank, James R.; Witczak, Steven C.; Winokur, Peter S.; Riewe, Leonard C.; Hash, Gerald L.

Abstract not provided.

Dodd, Paul E.; Shaneyfelt, Marty R.; Schwank, James R.; Hash, Gerald L.; Draper, Bruce L.; Winokur, Peter S.

SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed.

Shaneyfelt, Marty R.; Schwank, James R.; Witczak, Steven C.; Riewe, Leonard C.; Winokur, Peter S.; Hash, Gerald L.

Thermal-stress effects are shown to have a significant impact on the enhanced low-dose-rate sensitivity of linear bipolar circuits. Implications of these results on hardness assurance testing and mechanisms are discussed.