Substrate thinning is necessary in devices with flip-chip BGA packages to enable both radiation testing and component qualification and high-spatial resolution beam-based failure analysis methods. We investigated three factors affecting device performance: subsurface damage from the thinning process, reduced heat spreading in thin substrates, and changes in device switching speed. We conclude subsurface damage to crystalline Si caused by the thinning process is removable with sufficient SiO2 slurry polishing. Local temperature differences increase minimally in devices thinned to 3 μm. Compressive stress in the Si increases globally after device thinning and leads to slowing of ring oscillator frequency by about 0.5% compared to full-thickness devices. Future work will include extending the results to submicron Si thickness values, which also has important benefits for failure analysis, debug, and security assessments. We also plan to extend this type of work to other FPGAs and other devices like memory and processors.
Studies of size effects on thermal conductivity typically necessitate the fabrication of a comprehensive film thickness series. In this Letter, we demonstrate how material fabricated in a wedged geometry can enable similar, yet higher-throughput measurements to accelerate experimental analysis. Frequency domain thermoreflectance (FDTR) is used to simultaneously determine the thermal conductivity and thickness of a wedged silicon film for thicknesses between 100 nm and 17 μm by considering these features as fitting parameters in a thermal model. FDTR-deduced thicknesses are compared to values obtained from cross-sectional scanning electron microscopy, and corresponding thermal conductivity measurements are compared against several thickness-dependent analytical models based upon solutions to the Boltzmann transport equation. Our results demonstrate how the insight gained from a series of thin films can be obtained via fabrication of a single sample.
Maximum power handling, spike leakage, and failure mechanisms have been characterized for limiters based on the thermally triggered metal-insulator transition of vanadium dioxide. These attributes are determined by properties of the metal-insulator material such as on/off resistance ratio, geometric properties that determine the film resistance and the currentcarrying capability of the device, and thermal properties such as heatsinking and thermal coupling. A limiter with greater than 10 GHz of bandwidth demonstrated 0.5 dB loss, 27 dBm threshold power, 8 Watts blocking power, and 0.4 mJ spike leakage at frequencies near 2 GHz. A separate limiter optimized for high power blocked over 60 Watts of incident power with leakage less than 25 dBm after triggering. The power handling demonstrates promise for these limiter devices, and device optimization presents opportunities for additional improvement in spike leakage, response speed, and reliability.
Carrier lifetime and dark current measurements are reported for a mid-wavelength infrared InAs0.91Sb0.09 alloy nBn photodetector. Minority carrier lifetimes are measured using a non-contact time-resolved microwave technique on unprocessed portions of the nBn wafer and the Auger recombination Bloch function parameter is determined to be |F1F2|=0.292. The measured lifetimes are also used to calculate the expected diffusion dark current of the nBn devices and are compared with the experimental dark current measured in processed photodetector pixels from the same wafer. Excellent agreement is found between the two, highlighting the important relationship between lifetimes and diffusion currents in nBn photodetectors.
Conversion of plane waves to surface waves prior to detection allows key advantages in changes to the architecture of the detector pixels in a focal plane array. We have integrated subwavelength patterned metal nanoantennas with various detector materials to incorporate these advantages: midwave infrared indium gallium arsenide antimonide detectors and longwave infrared graphene detectors. Nanoantennas offer a means to make infrared detectors much thinner by converting incoming plane waves to more tightly bound and concentrated surface waves. Thinner architectures reduce both dark current and crosstalk for improved performance. For graphene detectors, which are only one or two atomic layers thick, such field concentration is a necessity for usable device performance, as single pass plane wave absorption is insufficient. Using III-V detector material, we reduced thickness by over an order of magnitude compared to traditional devices. We will discuss Sandia's motivation for these devices, which go beyond simple improvement in traditional performance metrics. The simulation methodology and design rules will be discussed in detail. We will also offer an overview of the fabrication processes required to make these subwavelength structures on at times complex underlying devices based on III-V detector material or graphene on silicon or silicon carbide. Finally, we will present our latest infrared detector characterization results for both III-V and graphene structures.