Publications

Abstract not provided.

Abstract not provided.

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

We have developed a complete process module for fabricating front end of line (FEOL) through silicon vias (TSVs). In this paper we describe the integration, which relies on using thermally deposited silicon as a sacrificial material to fill the TSV during FEOL processing, followed by its removal and replacement with tungsten after FEOL processing is complete. The uniqueness of this approach follows mainly from forming the TSVs early in the FEOL while still ultimately using metal as the via fill material. TSVs formed early in the FEOL can be formed at comparatively small diameter, high aspect ratio, and high spatial density. We have demonstrated FEOL-integrated TSVs that are 2 μm in diameter, over 45 μm deep, and on 20 μm pitch for a possible interconnect density of 250,000/cm2. Moreover, thermal oxidation of silicon can be used to form the dielectric isolation. Thermal oxidation is conformal and robust in the as-formed state. Finally, TSVs formed in the FEOL alleviate device design constraints common to vias-last integration. © 2009 IEEE.

Abstract not provided.

Abstract not provided.

Abstract not provided.