The design, fabrication, and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process that involved significant processing including the removal of the III-V substrate.
Here, we present a low resistance, straightforward planar ohmic contact for Al0.45Ga0.55N/Al0.3Ga0.7N high electron mobility transistors. Five metal stacks (a/Al/b/Au; a = Ti, Zr, V, Nb/Ti; b = Ni, Mo, V) were evaluated at three individual annealing temperatures (850, 900, and 950°C). The Ti/Al/Ni/Au achieved the lowest specific contact resistance at a 900°C anneal temperature. Transmission electron microscopy analysis revealed a metal-semiconductor interface of Ti-Al-Au for an ohmic (900°C anneal) and a Schottky (850°C anneal) Ti/Al/Ni/Au stack. HEMTs were fabricated using the optimized recipe with resulting contacts that had room-temperature specific contact resistances of ρc = 2.5 × 10-5 Ω cm², sheet resistances of RSH = 3.9 kΩ/$\blacksquare$, and maximum current densities of 75 mA/mm (at VGATE of 2 V). Electrical measurements from -50 to 200°C had decreasing specific contact resistance and increasing sheet resistance, with increasing temperature. These contacts enabled state-of-the-art performance of Al0.45Ga0.55N/Al0.3Ga0.7N HEMTs.
AlGaN-channel high electron mobility transistors (HEMTs) are among a class of ultra wide-bandgap transistors that have a bandgap greater than ~3.4 eV, beyond that of GaN and SiC, and are promising candidates for RF and power applications. Long-channel AlxGa1-xN HEMTs with x = 0.3 in the channel have been built and evaluated across the -50°C to +200°C temperature range. Room temperature drain current of 70 mA/mm, absent of gate leakage, and with a modest -1.3 V threshold voltage was measured. A very large Ion/Ioff current ratio, greater than 108 was demonstrated over the entire temperature range, indicating that off-state leakage is below the measurement limit even at 200°C. Finally, combined with near ideal subthreshold slope factor that is just 1.3× higher than the theoretical limit across the temperature range, the excellent leakage properties are an attractive characteristic for high temperature operation.
Varying atomic ratios in compound semiconductors is well known to have large effects on the etching properties of the material. The use of thin device barrier layers, down to 25 nm, adds to the fabrication complexity by requiring precise control over etch rates and surface morphology. The effects of bias power and gas ratio of BCl3 to Cl2 for inductively coupled plasma etching of high Al content AlGaN were contrasted with AlN in this study for etch rate, selectivity, and surface morphology. Etch rates were greatly affected by both bias power and gas chemistry. Here we detail the effects of small variations in Al composition for AlGaN and show substantial changes in etch rate with regards to bias power as compared to AlN.
An AlN barrier high electron mobility transistor (HEMT) based on the AlN/Al0.85Ga0.15N heterostructure was grown, fabricated, and electrically characterized, thereby extending the range of Al composition and bandgap for AlGaN channel HEMTs. An etch and regrowth procedure was implemented for source and drain contact formation. A breakdown voltage of 810 V was achieved without a gate insulator or field plate. Excellent gate leakage characteristics enabled a high Ion/Ioff current ratio greater than 107 and an excellent subthreshold slope of 75 mV/decade. A large Schottky barrier height of 1.74 eV contributed to these results. In conclusion, the room temperature voltage-dependent 3-terminal off-state drain current was adequately modeled with Frenkel-Poole emission.
Microsystems Enabled Photovoltaics (MEPV) is a relatively new field that uses microsystems tools and manufacturing techniques familiar to the semiconductor industry to produce microscale photovoltaic cells. The miniaturization of these PV cells creates new possibilities in system designs that can be used to reduce costs, enhance functionality, improve reliability, or some combination of all three. In this article, we introduce analytical tools and techniques to estimate the costs associated with a hybrid concentrating photovoltaic system that uses multi-junction microscale photovoltaic cells and miniaturized concentrating optics for harnessing direct sunlight, and an active c-Si substrate for collecting diffuse sunlight. The overall model comprises components representing costs and profit margin associated with the PV cells, concentrating optics, balance of systems, installation, and operation. This article concludes with an analysis of the component costs with particular emphasis on the microscale PV cell costs and the associated tradeoffs between cost and performance for the hybrid CPV design.
Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.
Microsystem-Enabled Photovoltaic (MEPV) cells allow solar PV systems to take advantage of scaling benefits that occur as solar cells are reduced in size. We have developed MEPV cells that are 5 to 20 microns thick and down to 250 microns across. We have developed and demonstrated crystalline silicon (c-Si) cells with solar conversion efficiencies of 14.9%, and gallium arsenide (GaAs) cells with a conversion efficiency of 11.36%. In pursuing this work, we have identified over twenty scaling benefits that reduce PV system cost, improve performance, or allow new functionality. To create these cells, we have combined microfabrication techniques from various microsystem technologies. We have focused our development efforts on creating a process flow that uses standard equipment and standard wafer thicknesses, allows all high-temperature processing to be performed prior to release, and allows the remaining post-release wafer to be reprocessed and reused. The c-Si cell junctions are created using a backside point-contact PV cell process. The GaAs cells have an epitaxially grown junction. Despite the horizontal junction, these cells also are backside contacted. We provide recent developments and details for all steps of the process including junction creation, surface passivation, metallization, and release.
Vapor phase XeF{sub 2} has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF{sub 2} Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF{sub 2} vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO{sub 2}) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF{sub 2} etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO{sub 2}. The buried SiO{sub 2} was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO{sub 2}. FC polymer was deposited from C4F8 gas precursor in an inductively coupled plasma reactor, and SiO{sub 2} was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF{sub 2} was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF{sub 2} due to protection from the top SiO{sub 2} mask, sidewall passivation, and the buried SiO{sub 2} layer. Optimization of the XeF{sub 2} process and the sidewall passivation layers will be discussed. The advantages of releasing SOI devices with XeF{sub 2} include avoiding stiction, maintaining the integrity of the buried SiO{sub 2}, and simplifying the fabrication flow for thermally actuated devices.
We present a newly developed microsystem enabled, back-contacted, shade-free GaAs solar cell. Using microsystem tools, we created sturdy 3 {micro}m thick devices with lateral dimensions of 250 {micro}m, 500 {micro}m, 1 mm, and 2 mm. The fabrication procedure and the results of characterization tests are discussed. The highest efficiency cell had a lateral size of 500 {micro}m and a conversion efficiency of 10%, open circuit voltage of 0.9 V and a current density of 14.9 mA/cm{sup 2} under one-sun illumination.
We present a newly developed microsystem enabled, back-contacted, shade-free GaAs solar cell. Using microsystem tools, we created sturdy 3 {micro}m thick devices with lateral dimensions of 250 {micro}m, 500 {micro}m, 1 mm, and 2 mm. The fabrication procedure and the results of characterization tests are discussed. The highest efficiency cell had a lateral size of 500 {micro}m and a conversion efficiency of 10%, open circuit voltage of 0.9 V and a current density of 14.9 mA/cm{sup 2} under one-sun illumination.