Publications
Self-voting dual-modular-redundancy circuits for single-event-transient mitigation
Dual-modular-redundancy (DMR) architectures use duplication and self-voting asynchronous circuits to mitigate single event transients (SETs). The area and performance of DMR circuitry is evaluated against conventional triple-modular-redundancy (TMR) logic. Benchmark ASIC circuits designed with DMR logic show a 1024% area improvement for flip-flop designs, and a 33% improvement for latch designs. © 2006 IEEE.