Publications

SEGR in SiO${}_2$ –Si$_3$ N$_4$ Stacks

Schwank, James R.; Shaneyfelt, Marty R.

This work presents experimental SEGR data for MOS-devices, where the gate dielectrics are are made of stacked SiO₂–Si₃N₄ structures. Also a semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is proposed. Then statistical interrelationship between SEGR cross-section data and simulated energy deposition probabilities in thin dielectric layers is discussed.