Publications
PV-Inverter Dynamic Model Validation and Comparison under Fault Scenarios Using a Power Hardware-in-the-Loop Testbed
The increasing penetration of inverter-interfaced resources underscores the need of valid and accurate pv-inverter models for short circuit studies and for the design of proper protection schemes. This paper presents comparison and validation of several inverter models' dynamics under fault scenarios to two commercial inverters using a Power Hardware-in-the-Loop (PHIL) testbed. Nowadays, IEEE1574 compliant inverters with anti-islanding will contribute for several cycles (1.1 p.u.) before they disconnect. As the inverter standards move towards low voltage ride-through (LVRT) capabilities to counteract remote faults, the accurate modeling of inverters using this feature becomes extremely important. One of the purposes of this paper is to compare the dynamic behavior of different inverter models with LVRT capabilities against two commercial inverters with the aid of PHIL simulation environments. Comparisons were made under different fault scenarios using the IEEE 13 node feeder as testing grid. The other purpose is to raise awareness amongst inverter manufacturers on providing accurate and comprehensive inverter simulation models that account for the protection engineers necessities.