Publications

DFF Layout Variations in CMOS SOI -Analysis of Hardening by Design Options

Black, Jeffrey B.; Black, Dolores A.; Domme, Nicholas A.; Dodd, Paul E.; Griffin, Patrick J.; Nowlin, R.N.; Trippe, James M.; Salas, Joseph G.; Reed, Robert A.; Weller, Robert A.; Tonigan, Andrew M.; Schrimpf, Ronald D.

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories' CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.