Publications

We seek to understand which supercomputer architecture will be best for supercomputers at the Petaflops scale and beyond. The process we use is to predict the cost and performance of several leading architectures at various years in the future. The basis for predicting the future is an expanded version of Moore's Law called the International Technology Roadmap for Semiconductors (ITRS). We abstract leading supercomputer architectures into chips connected by wires, where the chips and wires have electrical parameters predicted by the ITRS. We then compute the cost of a supercomputer system and the run time on a key problem of interest to the DOE (radiation transport). These calculations are parameterized by the time into the future and the technology expected to be available at that point. We find the new advanced architectures have substantial performance advantages but conventional designs are likely to be less expensive (due to economies of scale). We do not find a universal ''winner'', but instead the right architectural choice is likely to involve non-technical factors such as the availability of capital and how long people are willing to wait for results.

PIM (Processor in Memory) architectures are being proposed for future supercomputers, because they reduce the problems that SMP MMPs have with latency. However, they do not meet the SMP MPP balance factors. Being relatively processor rich and memory starved, it is unclear whether an ASCI application could run on them, either as-is or with recoding. The KBA (Koch-Baker-Alcouffe) algorithm (Koch, 1992) for particle transport (radiation transport) is shown not to fit on PIMs as written. When redesigned with a 3-D allocation of cells to PIMs, the resulting algorithm is projected to execute an order of magnitude faster and more cost-effectively than the KBA algorithm, albeit with high initial hardware costs.